參數(shù)資料
型號: QL3040-1PQ208M
廠商: QUICKLOGIC CORP
元件分類: FPGA
英文描述: 40000 usable PLD gate pASIC 3 FPGA combining High performance and high density
中文描述: FPGA, 1008 CLBS, 40000 GATES, 225 MHz, PQFP208
封裝: 28 X 28 MM, 3.35 MM HEIGHT, PLASTIC, MS-029, QFP-208
文件頁數(shù): 48/49頁
文件大?。?/td> 885K
代理商: QL3040-1PQ208M
www.quicklogic.com
2005 QuickLogic Corporation
pASIC 3 FPGA Family Data Sheet Rev. D
8
Power-Up Sequencing
Figure 5: Power-Up Requirements
When powering up a device, the VCC/VCCIO rails must take 400 s or longer to reach the maximum value
(refer to Figure 5).
NOTE: Ramping V
CC/VCCIO to the maximum voltage faster than 400 s can cause the device to behave
improperly.
For users with a limited power budget, keep (VCCIO -VCC)MAX ≤ 500 mV when ramping up the power supply.
Vol
tage
V
CCIO
V
CC
(V
CCIO -VCC)MAX
Time
400 us
V
CC
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