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參數(shù)資料
| 型號： | QL3040-0PQ240I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 226K |
| 代理商： | QL3040-0PQ240I |
276
Preliminary
8-276
QL3040 - pASIC 3 FPGATM
Clock Cells
I/O Cells
Notes:
[7] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44
half columns, each driven by an independent buffer. The number of half columns used does not affect clock
buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half
column.
[8] The following loads are used for tPXZ:
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column [7]
12348
10
11
tACK
Array Clock Delay
1.2
1.3
1.5
1.6
1.7
tGCKP
Global Clock Pin Delay
0.7
tGCKB
Global Clock Buffer Delay
0.8
0.9
1.1
1.2
1.3
Symbol
Parameter
Propagation Delays (ns)
Fanout [5]
12
3
4
8
10
tI/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
tISU
Input Register Set-Up Time
3.1
tIH
Input Register Hold Time
0.0
tlOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
tlORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
tlESU
Input Register clock Enable Set-Up Time
2.3
tlEH
Input Register Clock Enable Hold Time
0.0
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
30
50
75
100
150
tOUTLH
Output Delay Low to High
2.1
2.5
3.1
3.6
4.7
tOUTHL
Output Delay High to Low
2.2
2.6
3.2
3.7
4.8
tPZH
Output Delay Tri-state to High
1.2
1.7
2.2
2.8
3.9
tPZL
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
4.2
tPHZ
Output Delay High to Tri-State [8]
2.0
tPLZ
Output Delay Low to Tri-State [8]
1.2
5 pF
1K
5 pF
1K
tPHZ
tPLZ
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| QL3040-1PQ240C | Field Programmable Gate Array (FPGA) |
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相關(guān)代理商/技術(shù)參數(shù) |
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| QL3040-1PB456C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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| QL3040-1PQ208C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA|1008-CELL|CMOS|QFP|208PIN|PLASTIC |
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