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參數(shù)資料
| 型號(hào)： | QL24x32B |
| 廠(chǎng)商： | QuickLogic Corp. |
| 英文描述： | pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 帕希奇1家庭技術(shù)ViaLink？技術(shù)非常高速的CMOS的FPGA（帕希奇1系列技術(shù)ViaLink？技術(shù)超高速的CMOS現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 186K |
| 代理商： | QL24X32B |
pASIC 1 FAMILY
4-3
The pASIC 1 internal logic cell, shown in Figure 2, is a general-purpose
building block that can implement most TTL and gate array macro library
functions. It has been optimized to maintain the inherent speed advantage
of the ViaLink technology while ensuring maximum logic flexibility. The
logic cell consists of two 6-input AND gates, four 2-input AND gates,
three 2-to-1 multiplexers and a D flip-flop. Multiple outputs from the
logic cell allow the automatic place and route software to pack unrelated
logic functions into a single cell to maximize silicon utilization.
The pASIC 1 logic cell is unique among FPGA architectures in that it
offers up to 14-input-wide gating functions. This allows many logic
functions to be accomplished in a single cell delay that require two or
more delays with other architectures. It can implement all possible
Boolean transfer functions of up to three variables as well as many
functions of up to 14 variables
The multiplexer output feeds the D-type flip-flop which can also be
configured to provide J-K, S-R, or T-type functions. Two independent
SET and RESET inputs can be used to asynchronously control the output
condition.
p
4
FIGURE 1
A Matrix of Logic
Cells and Wiring
Channels
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