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參數(shù)資料
| 型號： | QL2009-XPF144I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| 中文描述： | 3.3V和5.0V帕希奇？ 2 FPGA的結(jié)合速度，密度，低成本和靈活性 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 272K |
| 代理商： | QL2009-XPF144I |
QL2009
3-45
Clock Cells
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column
[10]
2
3
4
2.2
2.3
2.4
1.2
1.2
1.2
1.6
1.6
1.7
1
8
10
2.6
1.2
1.9
13
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
2.2
1.2
1.5
2.5
1.2
1.8
1.2
2.0
I/O Cells
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
50
75
3.0
3.6
3.3
3.9
2.6
3.1
3.3
4.1
30
2.6
2.8
2.1
2.6
2.9
3.3
100
4.1
4.5
3.7
4.9
150
5.2
5.7
4.8
6.5
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [11]
Output Delay Low to Tri-State [11]
Notes:
[10]
The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
The following loads are used for tPXZ:
[11]
5 pF
1K
5 pF
1K
tPHZ
tPLZ
Symbol
Parameter
Propagation Delays (ns)
Fanout
[8]
2
3
2.1
2.4
4.8
4.8
0.0
0.0
1.1
1.4
1.0
1.3
4.1
4.1
0.0
0.0
1
4
8
10
4.6
4.8
0.0
3.6
3.5
4.1
0.0
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.8
4.8
0.0
0.8
0.7
4.1
0.0
2.7
4.8
0.0
1.7
1.6
4.1
0.0
3.9
4.8
0.0
2.9
2.8
4.1
0.0
p
3
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