- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361286 > QL2007 (QuickLogic Corp.) 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可適應(yīng)性強的3.3V和5.0V pASIC 2系列場可編程邏輯器件) PDF資料下載
參數(shù)資料
| 型號： | QL2007 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可適應(yīng)性強的3.3V和5.0V pASIC 2系列場可編程邏輯器件) |
| 中文描述： | 3.3V和5.0V帕希奇2 FPGA的結(jié)合速度，密度，低成本和靈活性（高速，高可用密度，低成本，可適應(yīng)性強的3.3和5.0V帕希奇2系列場可編程邏輯器件） |
| 文件頁數(shù)： | 10/10頁 |
| 文件大小： | 297K |
| 代理商： | QL2007 |
QL2007
3-34
Clock Cells
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column
[10]
2
3
4
2.2
2.3
2.4
1.2
1.2
1.2
1.6
1.6
1.7
1
8
10
2.6
1.2
1.9
13
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
2.2
1.2
1.5
2.5
1.2
1.8
1.2
2.0
I/O Cells
Symbol
Parameter
Propagation Delays (ns)
Fanout
[8]
2
3
2.1
2.4
4.8
4.8
0.0
0.0
1.1
1.4
1.0
1.3
4.1
4.1
0.0
0.0
1
4
8
10
4.6
4.8
0.0
3.6
3.5
4.1
0.0
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.8
4.8
0.0
0.8
0.7
4.1
0.0
2.7
4.8
0.0
1.7
1.6
4.1
0.0
3.9
4.8
0.0
2.9
2.8
4.1
0.0
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
50
75
3.0
3.6
3.3
3.9
2.6
3.1
3.3
4.1
30
2.6
2.8
2.1
2.6
2.9
3.3
100
4.1
4.5
3.7
4.9
150
5.2
5.7
4.8
6.5
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [11]
Output Delay Low to Tri-State [11]
Notes:
[10]
The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
The following loads are used for tPXZ:
[11]
5 pF
1K
5 pF
1K
tPHZ
tPLZ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL2009 | 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可適應(yīng)性強的3.3V和5.0V pASIC 2系列場可編程邏輯器件) |
| QL2009-0PB256C | 3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2009-0PB256I | PT 6C 6#20 PIN RECP |
| QL2009-0PF144C | 3.3V and 5.0V pASIC? 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2009-0PF144I | PT 8C 8#20 PIN RECP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL2007-0PF144C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL2007-0PF144I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL2007-0PL84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
| QL2007-0PL84C-3036 | 制造商:QuickLogic Corporation 功能描述: |
| QL2007-0PL84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。