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參數(shù)資料
| 型號： | QL1P100-7PU86M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| 封裝： | 6 X 6 MM, 1.20 MMHEIGHT, 0.50 MM PITCH, TFBGA-86 |
| 文件頁數(shù)： | 32/44頁 |
| 文件大?。?/td> | 1101K |
| 代理商： | QL1P100-7PU86M |
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2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100
38
Pin Descriptions
Table 40: Pin Descriptions
Pin
Direction
Function
Description
Dedicated Pin Descriptions
GPIO(C:A)
I/O
General purpose
input/output pin
The I/O pin is a bi-directional pin, configurable to either an
input-only, output-only, or bi-directional pin. The letter
inside the parenthesis means that the I/O is located in the
bank with that letter. If an I/O is not used, the development
software provides the option of tying that pin to GND,
VCCIO, or Hi-Z.
CLK(C:A)
I
Global clock network pin low
skew global clock
This pin provides access to a distributed network capable
of driving the CLOCK, SET, RESET, all inputs to the Logic
Cell, READ and WRITE CLOCKS, Read and Write
Enables of the Embedded RAM Blocks, and I/O inputs.
The voltage tolerance of this pin is specified by
VCCIO(C:A).
DEDCLK(D)
I
Dedicated clock network pin
low skew clock
This pin provides access to a distributed network capable
of driving the CLOCK, SET, RESET, all inputs to the Logic
Cell, READ and WRITE CLOCKS, Read and Write
Enables of the Embedded RAM Blocks, and I/O inputs.
The voltage tolerance of this pin is specified by
VCCIO(D).
CCMIN(1:0)
I
CCM clock input
Input clock for CCM. The voltage tolerance for this pin is
specified by the VCCIO of the same bank.
CCMVCC (1:0)
I
Power supply pin for CCM
CCM input voltage level. Configurable as 1.8 V only.
CCMGND(1:0)
I
Ground pin for CCM
Connect to ground.
VLP
I
Voltage low power
Active low. Therefore, when VLP pin is low, the device will
go into low power mode. Tie VLP to 3.3 V to disable low
power mode.
VCC
I
Power supply pin
Connect to 1.8 V supply.
VCCIO(D:A)
I
Input voltage tolerance pin
This pin provides the flexibility to interface the device with
either a 3.3 V, 2.5 V, or 1.8 V device. The letter inside the
parenthesis means that the VCCIO is located in the bank
with that letter. Every I/O pin in the same bank will be
tolerant of the same VCCIO input signals and will drive
VCCIO level output signals. This pin must be connected
to either 3.3 V, 2.5 V, or 1.8 V.
GND
I
Ground pin
Connect to ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL1P100-7PUN86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86I | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-7PUN86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86C | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
| QL1P100-8PU86M | FPGA, 640 CLBS, 100000 GATES, PBGA86 |
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