參數(shù)資料
型號(hào)： QL1P100-6PUN86I
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 100000 GATES, PBGA86
封裝： 6 X 6 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, TFBGA-86
文件頁(yè)數(shù)： 31/44頁(yè)
文件大小： 1101K
代理商： QL1P100-6PUN86I
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
37
Power-Up Sequencing
Figure 31: Power-Up Sequencing
Figure 31 shows an example where all VCCIO = 3.3 V. When powering up a PolarPro device, VCC, VCCIO
rails must take 10 s or longer to reach the maximum value (refer to Figure 31). Ramping VCC and VCCIO
faster than 10 s can cause the device to behave improperly
.
It is also important to ensure VCCIO and VLP are within 500 mV of VCC when ramping up the power
supplies. In the case where VCCIO or VLP are greater than VCC by more than 500 mV an additional current
draw can occur as VCC passes its threshold voltage. In a case where VCC is greater than VCCIO by more
than 500 mV the protection diodes between the power supplies become forward biased. If this occurs then
there will be an additional current load on the power supply. Having the diodes on can cause a reliability
problem, since it can wear out the diodes and subsequently damage the internal transistors. As noted in the
VLP section, during the transition from VLP mode to normal operation, the VLP pin can draw up to 1.5 mA.
Consequently, if using a pull-up resistor, use a pull-up resistor with a value that is less than 2 K
.
Programming Stipulation
For PolarPro devices to correctly program, there must not be any race conditions or internally generated free-
running oscillators in the design. This will cause an ICC programming failure during the programming process.
QuickLogic cannot guarantee the operation of any device that fails programming. Therefore, race conditions
and free-running oscillators must be removed from designs so that PolarPro devices can correctly pass
programming.
Vo
ltag
e
V
CCIO ,VLP
V
CC
|V
CCIO - VCC| MAX
Time
10 us
V
CC
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