參數(shù)資料
型號(hào)： QL1P100-6PU86C
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 100000 GATES, PBGA86
封裝： 6 X 6 MM, 1.20 MMHEIGHT, 0.50 MM PITCH, TFBGA-86
文件頁(yè)數(shù)： 5/44頁(yè)
文件大?。?/td> 1101K
代理商： QL1P100-6PU86C
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100 Rev. G
13
Configurable Clock
Manager (CCM)
The CCM features include:
Input frequency range from 10 MHz to 200 MHz
Output frequency range from 25 MHz to 200 MHz
Output jitter is less than 200 ps peak-to-peak
Two outputs: pullout0 (with 0° phase shift), and pullout1 (with an option of 0°, 90°, 180°, or 270° phase
shift plus a programmable delay).
Programmable delay allows delays up to 2.5 ns at 250 ps intervals
Fixed feedback path
Output frequency lock time in less than 10 s
Figure 12: Configurable Clock Manager
The reset signal can be routed from a clock pad or generated using internal logic. The lock_out signal can be
routed to internal logic and/or an output pad. CCM clock outputs can drive the global clock networks, as well
as any general purpose I/O pin. Once the CCM has synchronized the output clock to the incoming clock, the
lock_out signal will be asserted to indicate that the output clock is valid. Lock detection requires at least 10 s
after reset to assert lock_out. The PolarPro CCMs have three modes of operation, based on the input
frequency and desired output frequency. Table 11 indicates the features of each mode.
Table 11: CCM PLL Mode Frequencies
Output
Frequency
Input Frequency
Range
Output Frequency
Range
PLL Mode
x1
25 MHz to 200 MHz
PLL_MULT1
x2
15 MHz to 100 MHz
30 MHz to 200 MHz
PLL_MULT2
x4
10 MHz to 50 MHz
40 MHz to 200 MHz
PLL_MULT4
pllout0
ded_in
pgm_in
fin_cnt
ded_fd
pgm_fd
fd_cnt
rst_in
fc[1:0]
s[1:0]
tdctl[3:0]
pllout1
lock_out
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