參數(shù)資料
型號: Q67121-C942
廠商: SIEMENS AG
英文描述: 16-Bit CMOS Single-Chip Microcontroller
中文描述: 16位CMOS單芯片微控制器
文件頁數(shù): 25/69頁
文件大小: 1124K
代理商: Q67121-C942
Semiconductor Group
25
1997-07-01
C515C
SSC
Interface
SSCCON
STB
SRB
SCF
SCIEN
SSCMOD
SSC Control Register
SSC Transmit Buffer
SSC Receive Register
SSC Flag Register
SSC Interrupt Enable Register
SSC Mode Test Register
93H
94H
95H
ABH
ACH
96H
88H
8CH
8DH
8AH
8BH
89H
C1H
C3H
C5H
C7H
C2H
C4H
C6H
CBH
CAH
CDH
CCH
C8
H
86H
A8H
B8H
A9H
87H
88H
1
)
1
)
07H
XXH
XXH
XXXXXX00B
XXXXXX00B
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
0XXXXXXXB
3
)
3
)
3)
3)
Timer 0/
Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
1)
Compare/
Capture
Unit /
Timer 2
CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON
Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register
1)
Watchdog WDTREL
IEN0
2)
IEN1
2)
IP0
2)
Watchdog Timer Reload Register
Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
1)
1)
Power
Save
Modes
PCON
2)
PCON1
Power Control Register
Power Control Register 1
4)
3)
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Table 3
Special Function Registers - Functional Blocks (cont’d)
Block
Symbol
Name
Address
Contents after
Reset
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