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參數資料
| 型號： | Q67120-C2043 |
| 廠商： | SIEMENS AG |
| 英文描述： | High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker 14-SOIC -55 to 125 |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數： | 9/24頁 |
| 文件大小： | 980K |
| 代理商： | Q67120-C2043 |
C167CS-xC Bare Die
Step BA
Data Sheet
5
V1.0, 2001-08
Table 2
Pad Definitions and Functions
Symbol Pad
Num
In /
Out
Position
[μm]
Function
x
305
460
615
y
0 Reference voltage for the A/D converter.
0 Reference ground for the A/D converter.
0 Port 5 input, analog input AN10,
external up/down T6EUD.
0 Port 5 input, analog input AN11,
external up/down T5EUD.
0 Port 5 input, analog input AN12,
timer input T6IN.
0 Port 5 input, analog input AN13,
timer input T5IN.
0 Port 5 input, analog input AN14,
external up/down T4EUD.
0 Port 5 input, analog input AN15,
external up/down T2EUD.
0 Digital Ground.
0 Digital Supply Voltage.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC0IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC1IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC2IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC3IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC4IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC5IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC6IO.
0 Port 2 input/output (open drain, sp. threshold),
Capture-Input/Compare-Output CC7IO.
AREF
1
2
3
-
-
I
AGND
P5.10
P5.11
4
I
770
P5.12
5
I
925
P5.13
6
I
1081
P5.14
7
I
1236
P5.15
8
I
1391
SS
9
10
11
-
-
I/O
1563
1688
1960
DD
P2.0
P2.1
12
I/O
2139
P2.2
13
I/O
2318
P2.3
14
I/O
2497
P2.4
15
I/O
2676
P2.5
16
I/O
2855
P2.6
17
I/O
3034
P2.7
18
I/O
3214
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