HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
18
12.99
Refresh Period
(4096 cycles)
t
REF
–
64
–
64
ms
–
Self Refresh Exit Time
t
SREX
1
–
1
–
CLK
6
Read Cycle
Data Out Hold Time
t
OH
t
LZ
t
HZ
t
DQZ
3
–
3
–
ns
2
Data Out to Low Impedance Time
1
–
0
–
ns
–
Data Out to High Impedance Time
3
7
3
8
ns
–
DQM Data Out Disable Latency
–
2
–
2
CLK
–
Write Cycle
Write Recovery Time
t
WR
t
DQW
2
–
2
–
CLK
–
DQM Write Mask Latency
0
–
0
–
CLK
–
AC Characteristics
(cont’d)
1, 2
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symb.
Limit Values
Unit
Note
-7.5
-8
min.
max.
min.
max.