參數(shù)資料
型號： Q67100-Q2800
廠商： INFINEON TECHNOLOGIES AG
英文描述： BAG 8X10 SHIELDED ZIP LOCK
中文描述： 64兆位同步DRAM
文件頁數(shù)： 8/53頁
文件大小： 418K
代理商： Q67100-Q2800
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
8
12.99
DQM
LDQM
UDQM
Input
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input it present in
×
4 and
×
8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in
×
16
SDRAMs.
V
DD
V
SS
Supply
–
–
Power and ground for the input buffers and the core logic.
V
DDQ
V
SSQ
Supply –
–
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
V
REF
Input
Level
–
Reference voltage for SDRAM versions supporting SSTL
interface
Signal Pin Description
(cont’d)
Pin
Type
Signal Polarity Function
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
Q67100-Q3016 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 36-Bit EDO-DRAM Module
Q67100-Q3017 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:4M x 36-Bit EDO-DRAM Module
Q67100-Q3018 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8M x 36-Bit EDO-DRAM Module
Q67100-Q3019 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:8M x 36-Bit EDO-DRAM Module
Q67100-Q433 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 K x 4-Bit Dynamic RAM Low Power 256 K x 4-Bit Dynamic RAM
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