參數(shù)資料
型號(hào)： Q67100-H6301
廠商： SIEMENS AG
英文描述： Memory Time Switch Large MTSL
中文描述： 內(nèi)存定時(shí)開(kāi)關(guān)大型MTSL
文件頁(yè)數(shù)： 17/53頁(yè)
文件大?。?/td> 418K
代理商： Q67100-H6301
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
17
12.99
AC Characteristics
1, 2
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
DD
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symb.
Limit Values
Unit
Note
-7.5
-8
min.
max.
min.
max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
t
CK
7.5
10
–
–
8
10
–
–
ns
ns
–
Clock Frequency
CAS Latency = 3
CAS Latency = 2
t
CK
133
100
–
–
–
–
125
100
MHz
MHz
–
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
t
AC
–
–
5.4
6
–
–
6
6
ns
ns
2, 3
Clock High Pulse Width
t
CH
t
CL
t
T
2.5
–
3
–
ns
–
Clock Low Pulse Width
2.5
–
3
–
ns
–
Transition Time
0.3
1.2
0.5
10
ns
–
Setup and Hold Times
Input Setup Time
t
IS
t
IH
t
CKS
t
CKH
t
RSC
t
SB
1.5
–
2
–
ns
4
Input Hold Time
0.8
–
1
–
ns
4
CKE Setup Time
1.5
–
2
–
ns
4
CKE Hold Time
0.8
–
1
–
ns
4
Mode Register Set-up Time
2
–
2
–
CLK
–
Power Down Mode Entry Time
0
7
0
8
ns
–
Common Parameters
Row to Column Delay Time
t
RCD
t
RP
t
RAS
t
RC
t
RRD
20
–
20
–
ns
5
Row Precharge Time
20
–
20
–
ns
5
Row Active Time
45
100k
48
100k
ns
5
Row Cycle Time
67
–
70
–
ns
5
Activate(a) to Activate(b) Command
Period
14
–
16
–
ns
5
CAS(a) to CAS(b) Command Period
t
CCD
1
–
1
–
CLK
–
Refresh Cycle
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