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參數(shù)資料
| 型號： | Q67001-A5214 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Components for Entertainment Electronics, Satellite Sound IF |
| 中文描述： | 元件娛樂電子，衛(wèi)星聲音中頻 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大?。?/td> | 416K |
| 代理商： | Q67001-A5214 |
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Data Sheet
TDA6170X
Semiconductor Group
19
21.7.99
total harmonic distortion
THD
0.2
0.5
%
V
MIXIN
> 2 mV
f = 27kHz,
f
mod
= 1kHz,
Control Byte = 000
0.2
0.5
%
V
MIXIN
> 2 mV
f = 50kHz,
f
mod
= 1kHz,
Control Byte = 011
signal to noise ratio
S/N
70
75
dB
A-weighted,
f = 27kHz,
f
mod
= 1kHz,
Control Byte = 000
Mute attenuation
a
MUTE
75
90
dB
Control Byte = 111
I
2
C-Bus Interface
LOW level input voltage for both
SDA and SCL
V
IL
-0.5
1.5
V
HIGH level input voltage for both
SDA and SCL
V
IH
3
V
VD
+
0.5
V
Hysteresis of Schmitt trigger
inputs
V
hys
0.2
V
Pulse width of spikes which must
be suppressed by the input filters
t
SP
50
ns
LOW level output voltage (open
collector)
V
OL1
V
OL2
0
0
0.4
0.6
V
3 mA sink current
6 mA sink current
Output fall time from
V
IHmin
to V
ILmax
with a bus
capacitance from 10 pF to 400 pF
t
OF
20 +
0.1C
b
250
ns
Input current for both SDA + SCL
I
i
-10
10
μ
A
SCL clock frequency
f
SCL
0
400
kHz
Bus free time between a STOP
and START condition
t
BUF
1.3
μ
s
Hold time (repeated) START con-
dition. After this period, the first
clock pulse is generated
t
HD,STA
0.6
μ
s
LOW period of the SCL clock
t
LOW
1.3
μ
s
HIGH period of the SCL clock
t
HIGH
0.6
μ
s
Set-up time for repeated START
condition
t
SU,DAT
0.6
μ
s
Data hold time:
for I
2
C-bus devices
t
HD,DAT
0
0.9
μ
s
Data set-up time
t
SU,DAT
100
ns
Rise time of both SDA + SCL
t
R
20 +
0.1C
b
300
ns
Parameter
Symbol
Limit Values
Unit
Test conditions
min
typ
max
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