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參數(shù)資料
| 型號： | Q67000-A8368-A205 |
| 廠商： | SIEMENS AG |
| 英文描述： | RECTIFIER STANDARD SINGLE 1A 1000V 1000 30A-ifsm 5uA-ir 1V-vf A405 5K/REEL-13 |
| 中文描述： | 功率因數(shù)控制器功率因數(shù)校正集成電路高功率因數(shù)，有源諧波濾波器 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 194K |
| 代理商： | Q67000-A8368-A205 |
TDA 4862
Semiconductor Group
4
1998-02-16
Functional Description
Introduction
Conventional electronic ballasts and switching power supplies are designed with a
bridge rectifier and bulk capacitor. Their disadvantage is that the circuit draws power
from the line when the instantaneous AC voltage exceeds the capacitor’s voltage. This
occurs near the line voltage peak and causes a high charge current spike with following
characteristics: the apparent power is higher than the real power that means low power
factor condition, the current spikes are non-sinusoidal with a high content of harmonics
causing line noise, the rectified voltage depends on load condition and requires a large
bulk capacitor, special efforts in noise suppression are necessary.
With the TDA 4862 preconverter a sinusoidal current is achieved which varies in direct
instantaneous proportion to the input voltage half sine wave and means a power factor
near 1. This is due to the appearance of almost any complex load like a resistive one at
the AC line. The harmonic distortions are reduced and comply with the IEC555 standard.
Operating Description
The TDA 4862 contains a wide bandwidth voltage amplifier used in a feedback loop, an
overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a
current sense comparator, zero current detector, a PWM and logic circuitry, a totem-pole
MOSFET driver, an internal trimmed voltage reference, a restart timer and an
undervoltage lockout circuitry. These functional blocks are described below.
Voltage Amplifier
The voltage amplifier is internally compensated and yields a gain bandwidth of 0.8 MHz
and a phase margin of 80 degrees. The non-inverting input is biased at 2.5 V and is not
pinned out. The inverting input is sensing the output voltage via a resitive devider. The
voltage amplifier output
V
AOUT
and the inverting input
V
SENSE
are connected in a simplest
way via an external capacitor. It forms an integrator which monitors the average output
voltage over several line cycles. Typically the bandwidth is set below 20 Hz. ln order to
keep the output voltage constant the voltage amplifier output is connected to the
multiplier input for regulation.
Overvoltage Regulator
Fast changes of the output voltage can’t be regulated by the integrator formed with the
voltage amplifier This occurs during initial start-up, sudden load removal, or output
arcing and leads to a current peak at the voltage amplifier input while the voltage
amplifier’s differential input voltages remains zero. The peak current is flowing through
the external capacitor into
V
AOUT
. Exceeding an internal defined margin causes a
regulation circuitry to reduce the multiplier output voltage.
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