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參數(shù)資料
| 型號(hào)： | PZ5128NS15BE |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 180K |
| 代理商： | PZ5128NS15BE |
Philips Semiconductors
Product specification
PZ5128
128 macrocell CPLD
1997 Aug 12
5
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
the 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t
PD
of the PZ5128 device through the PAL array is
7.5ns. If a macrocell needs more than 5 product terms, it simply gets
the additional product terms from the PLA array. The PLA array
consists of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2ns. So the
total pin-to-pin t
PD
for the PZ5128 using 6 to 37 product terms is
9.5ns (7.5ns for the PAL + 2ns for the PLA).
T
6
5
CONTROL
PAL
ARRAY
36 ZIA INPUTS
PLA
ARRAY
(32)
SP00435
Figure 2.
Philips Logic Block Architecture
相關(guān)PDF資料 |
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| PZ5128NS15BE-S | Electrically-Erasable Complex PLD |
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| PZ5128-S10A84 | Electrically-Erasable Complex PLD |
| PZ5128-S10BB1 | Electrically-Erasable Complex PLD |
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