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| 型號： | PZ3128-S15BE-S |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 161K |
| 代理商： | PZ3128-S15BE-S |
R
XCR3128: 128 Macrocell CPLD
DS034 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
4
This product has been discontinued. Please see
for details.Macrocell Architecture
Figure 3
shows the architecture of the macrocell used in
the CoolRunner family. The macrocell consists of a flip-flop
that can be configured as either a D- or T-type. A D-type
flip-flop is generally more useful for implementing state
machines and data buffering. A T-type flip-flop is generally
more useful in implementing counters. All CoolRunner fam-
ily members provide both synchronous and asynchronous
clocking and provide the ability to clock off either the falling
or rising edges of these clocks. These devices are
designed such that the skew between the rising and falling
edges of a clock are minimized for clocking integrity. There
are four clocks available on the XCR3128 device. Clock 0
(CLK0) is designated as the "synchronous" clock and must
be driven by an external source. Clock 1 (CLK1), Clock 2
(CLK2), and Clock 3 (CLK3) can either be used as a syn-
chronous clock (driven by an external source) or as an
asynchronous clock (driven by a macrocell equation). The
timing for asynchronous clocks is different in that the t
CO
time is extended by the amount of time that it takes for the
signal to propagate through the array and reach the clock
network, and the t
SU
time is reduced.
Two of the control terms (CT0 and CT1) are used to control
the Preset/Reset of the macrocell
’
s flip-flop. The Pre-
set/Reset feature for each macrocell can also be disabled.
Note that the Power-on Reset leaves all macrocells in the
"zero" state when power is properly applied. The other four
control terms (CT2-CT5) can be used to control the Output
Enable of the macrocell
’
s output buffers. The reason there
are as many control terms dedicated for the Output Enable
of the macrocell is to insure that all CoolRunner devices are
PCI compliant. The macrocell
’
s output buffers can also be
always enabled or disabled. All CoolRunner devices also
provide a Global 3-state (GTS) pin, which, when enabled
and pulled Low, will 3-state all the outputs of the device.
This pin is provided to support "In-circuit Testing" or
"Bed-of-nails" testing.
There are two feedback paths to the ZIA: one from the
macrocell, and one from the I/O pin. The ZIA feedback path
before the output buffer is the macrocell feedback path,
while the ZIA feedback path after the output buffer is the I/O
pin ZIA path. When the macrocell is used as an output, the
output buffer is enabled, and the macrocell feedback path
can be used to feedback the logic implemented in the mac-
rocell. When the I/O pin is used as an input, the output
buffer will be 3-stated and the input signal will be fed into
the ZIA via the I/O feedback path, and the logic imple-
mented in the buried macrocell can be fed back to the ZIA
via the macrocell feedback path. It should be noted that
unused inputs or I/Os should be properly terminated (see
the section on
“
Terminations
”
on page 9
in this data sheet
and the application note
Terminating Unused I/O Pins in
Xilinx XPLA1 and XPLA2 CoolRunner
CPLDs
).
Figure 3: XCR3128 Macrocell Architecture
CT2
CT3
CT4
CT5
V
CC
GND
INIT
(P or R)
D/T
Q
CLK0
CLK0
CLK1
CLK1
PAL
LA
TO ZIA
GND
CT0
CT1
GND
GTS
CLK2
CLK2
CLK3
CLK3
SP00457
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