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參數(shù)資料
| 型號： | PXAS83XFA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | XA 16-bit microcontroller(XA 16位微控制器) |
| 中文描述： | 16-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PEDESTAL, PLASTIC, MO-047AE, SOT-188-3, LCC-68 |
| 文件頁數(shù)： | 19/52頁 |
| 文件大?。?/td> | 281K |
| 代理商： | PXAS83XFA |
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Philips Semiconductors
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
2000 Mar 09
19
CR0, CR1, and CR2, the Clock Rate Bits
These three bits determine the serial clock frequency when the I
2
C
interface is in a master mode. An I
2
C rate of 100kHz or lower is
typical and can be derived from many oscillator frequencies. The
various serial rates are shown in Table 4. A variable bit rate may
also be used if Timer 1 is not required for any other purpose while
the I
2
C hardware is in a master mode. The frequencies shown in
Table 4 are unimportant when the I
2
C hardware is in a slave mode.
In the slave modes, the hardware will automatically synchronize with
the incoming clock frequency.
The I
2
C Status Register, I2STA
I2STA is an 8-bit read-only special function register. The three least
significant bits are always zero. The five most significant bits contain
the status code. There are 26 possible status codes. When I2STA
contains F8H, no relevant state information is available and no serial
interrupt is requested. All other I2STA values correspond to defined
hardware interface states. When each of these states is entered, a
serial interrupt is requested (SI = “1”).
NOTE: A detailed I
2
C interface description and usage
information, including example driver code, will be provided in
a separate document.
Table 4. I
2
C Rate Control
Frequency
(CR2, CR1, CR0)
Clock Divisor
Example I
2
C Rates at Specific Oscillator Frequencies
8 MHz
(400)
1
(200)
1
(116.65)
1
12 MHz
16 MHz
20 MHz
24 MHz
30 MHz
0h (0000)
20
–
–
–
–
–
1h (0001)
40
(300)
1
(176.46)
1
(136.36)
1
(400)
1
(235.29)
1
(181.82)
1
–
–
–
2h (0010)
68
(294.12)
1
(227.27)
1
(125)
1
(352.94)
1
(272.73)
1
(150)
1
–
3h (0011)
88
90.91
(340.91)
1
(187.5)
1
(110.29)
1
4h (0100)
160
50
75
100
5h (0101)
272
29.41
44.12
58.82
73.53
88.24
6h (0110)
352
22.73
(Timer 1)
2
34.09
(Timer 1)
2
45.45
(Timer 1)
2
56.82
(Timer 1)
2
68.18
(Timer 1)
2
85.23
(Timer 1)
2
7h (0111)
NOTES:
1. The XA-S3 I
2
C interface does not conform to the 400kHz I
2
C specification (which applies to rates greater than 100kHz) in all details, but
may be used with care where higher rates are required by the application.
2. The timer 1 overflow is used to clock the I
2
C interface. The resulting bit rate is 1/2 of the timer overflow rate.
(Timer 1)
2
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