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參數(shù)資料
| 型號： | PXAS30KFBE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | XA 16-bit microcontroller 32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage 2.7 V.5.5 V, I2C, 2 UARTs, 16 MB address range |
| 中文描述： | 16-BIT, 30 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 17/52頁 |
| 文件大?。?/td> | 295K |
| 代理商： | PXAS30KFBE |
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Philips Semiconductors
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
C, 2 UARTs, 16 MB address range
Preliminary specification
XA-S3
2000 Dec 01
17
A/D Accuracy
The XA-S3 A/D in 10 -bit mode is specified with 16 samples
averaged in order to factor out on-chip noise. In an application
where averaging 16 samples is not practical, the accuracy
specifications may be de-rated according to the number of samples
that are actually taken. The graph in Figure 5 shows the relationship
of additional A/D error to the number of samples that are averaged.
For example, if a single A/D reading is used with no averaging, the
A/D accuracy should be de-rated by
±
1.25 LSB.
SU01227
1.50
1.25
1.00
0.75
0.50
0.25
0.00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Number of Samples
A
Figure 5. A/D accuracy by number of averaging samples
(Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to f
C
= 20 MHz.)
CR0
LSB
MSB
BIT
I2CON.7
I2CON.6
I2CON.5
SYMBOL
CR2
ENA
STA
FUNCTION
I
2
C Rate Control, with CR1 and CR0. See text and table.
Enable I
2
C port. When ENA = 1, the I
2
C port is enabled.
Start flag. Setting STA to 1 causes the I
2
C interface to attempt to gain mastership of the bus by
generating a Start condition.
Stop flag. Setting STO to 1 causes the I
2
C interface to attempt to generate a Stop condition.
Serial Interrupt. SI is set by the I
2
C hardware when a new I
2
C state is entered, indicating that
software needs to respond. SI causes an I
2
C interrupt if enabled and of sufficient priority.
Assert Acknowledge. Setting AA to 1 causes the I
2
C hardware to automatically generate
acknowledge pulses for various conditions (see text).
I
2
C Rate Control, with CR2 and CR0. See text and table.
I
2
C Rate Control, with CR2 and CR1. See text and table.
I2CON.4
I2CON.3
STO
SI
I2CON.2
AA
I2CON.1
I2CON.0
CR1
CR0
CR1
AA
SI
STO
STA
ENA
CR2
I2CON
Bit Addressable
Reset Value: 00h
Address:42Ch
SU00941
Figure 6. I
2
C Control Register (I2CON)
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