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參數(shù)資料
| 型號： | PXAG37KBBD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | XA 16-bit microcontroller family 32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs |
| 中文描述： | 16-BIT, OTPROM, 30 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT389-1, LQFP-44 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 208K |
| 代理商： | PXAG37KBBD |
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Philips Semiconductors
Product specification
XA-G3
XA 16-bit microcontroller family
32K/512 OTP/ROM/ROMless, watchdog, 2 UARTs
1999 Apr 07
23
AC ELECTRICAL CHARACTERISTICS (5V)
V
DD
= 4.5V to 5.5V; T
amb
= 0 to +70
°
C for commercial, –40
°
C to +85
°
C for industrial.
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
MIN
MAX
External Clock
f
C
t
C
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Address Cycle
Oscillator frequency
0
30
MHz
22
Clock period and CPU timing cycle
1/f
C
t
C
* 0.5
t
C
* 0.4
ns
22
Clock high time
ns
22
Clock low time
ns
22
Clock rise time
5
ns
22
Clock fall time
5
ns
t
CRAR
t
LHLL
t
AVLL
t
LLAX
Code Read Cycle
21
Delay from clock rising edge to ALE rising edge
10
46
ns
16
ALE pulse width (programmable)
(V1 * t
C
) – 6
(V1 * t
C
) – 12
(t
C
/2) – 10
ns
16
Address valid to ALE de-asserted (set-up)
ns
16
Address hold after ALE de-asserted
ns
t
PLPH
t
LLPL
t
AVIVA
t
AVIVB
t
PLIV
t
PXIX
t
PXIZ
t
IXUA
Data Read Cycle
16
PSEN pulse width
(V2 * t
C
) – 10
(t
C
/2) – 7
ns
16
ALE de-asserted to PSEN asserted
ns
16
Address valid to instruction valid, ALE cycle (access time)
(V3 * t
C
) – 36
(V4 * t
C
) – 29
(V2 * t
C
) – 29
ns
17
Address valid to instruction valid, non-ALE cycle (access time)
ns
16
PSEN asserted to instruction valid (enable time)
ns
16
Instruction hold after PSEN de-asserted
0
ns
16
Bus 3-State after PSEN de-asserted (disable time)
t
C
– 8
ns
16
Hold time of unlatched part of address after instruction latched
0
ns
t
RLRH
t
LLRL
t
AVDVA
t
AVDVB
t
RLDV
t
RHDX
t
RHDZ
t
DXUA
Data Write Cycle
18
RD pulse width
(V7 * t
C
) – 10
(t
C
/2) – 7
ns
18
ALE de-asserted to RD asserted
ns
18
Address valid to data input valid, ALE cycle (access time)
(V6 * t
C
) – 36
(V5 * t
C
) – 29
(V7 * t
C
) – 29
ns
19
Address valid to data input valid, non-ALE cycle (access time)
ns
18
RD low to valid data in, enable time
ns
18
Data hold time after RD de-asserted
0
ns
18
Bus 3-State after RD de-asserted (disable time)
t
C
– 8
ns
18
Hold time of unlatched part of address after data latched
0
ns
t
WLWH
t
LLWL
t
QVWX
t
WHQX
t
AVWL
t
UAWH
Wait Input
20
WR pulse width
(V8 * t
C
) – 10
(V12 * t
C
) – 10
(V13 * t
C
) – 22
(V11 * t
C
) – 5
(V9 * t
C
) – 22
(V11 * t
C
) – 7
ns
20
ALE falling edge to WR asserted
ns
20
Data valid before WR asserted (data setup time)
ns
20
Data hold time after WR de-asserted (Note 6)
ns
20
Address valid to WR asserted (address setup time) (Note 5)
ns
20
Hold time of unlatched part of address after WR is de-asserted
ns
t
WTH
t
WTL
21
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
(V10 * t
C
) – 30
ns
21
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
(V10 * t
C
) – 5
ns
NOTES ON PAGE 24.
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