參數(shù)資料
型號(hào)： PXAC37KBA
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 16-bit microcontroller family(16位微控制器系列)
中文描述： 16-BIT, OTPROM, 32 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 53/68頁(yè)
文件大小： 344K
代理商： PXAC37KBA
Philips Semiconductors
Preliminary specification
XA-C3
XA 16-bit microcontroller family
32K/1024 OTP CAN transport layer controller
1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID filters, transport layer co-processor
2000 Jan 25
46
for transmission, regardless of the priority level represented by its
CAN identifier.
Message Retrieval
Once a Message Object is selected for transmission, the DMA will
begin retrieving the data from the message buffer area in memory
and transferring the data to the CAN core block for transmission.
The same DMA engine and address pointer logic is used for
message retrieval of transmit messages as for message storage of
receive messages. Message buffer location and size information is
specified in the same way. Please refer to the section entitled
Message Storageon page 41 for a complete description.
When a message is retrieved, it will be written to the CCB
sequentially. During this process, the DMA will keep requesting the
bus, reading from memory and writing to the CCB.
To prepare a message for transmission, the User application is
required to put the message in the appropriate object’s message
buffer area in the format shown below:
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Direction of increasing
address
Please observe that the CAN identifier field and frame info must not
be included in the transmit buffer. The transmit logic retrieves this
information from the appropriate MnMIDH, MnMIDL, and MnMSKH
registers. The format for storing the frame information in the
MnMSKH register is shown in Figure 42.
15
x
14
x
13
x
12
x
11
x
10
x
9
x
8
x
7
x
6
x
5
x
4
x
3
2
1
0
DLC.3
DLS.2
DLC.1
DLC.0
Figure 42. Format for Storing the Tx Frame Info in MnMSKH
Transmission of Fragmented Messages
The XA-C3 does not handle the transmission of Fragmented
messages in hardware. It is the User’s responsibility to write each
frame of a Fragmented message to the transmit buffer, enable the
object for transmission, and wait for a completion before writing the
next frame to the message buffer. The User application must
therefore transmit multiple frames one by one until the whole
message is transmitted.
However, by using multiple Tx objects whose object numbers
increase sequentially, and whose CAN IDs have been configured
identically, several frames of a Fragmented message can be
queued–up and enabled, and will be transmitted in order.
RTR Handling
This section describes how to receive or transmit Remote Transmit
Request (RTR) frames.
Receiving an RTR Frame
1. The software must setup an Rx object with the RTR bit in
MnCTL[0] set to ‘1’.
2. An RTR frame is received when the CAN ID Matches that of the
enabled receive object whose RTR bit set to ‘1’.
3. If interrupt is enabled for that Message Object, an interrupt will
be generated upon the RTR message reception.
4. The software would usually have a transmit object available with
the same ID. Upon receiving an RTR frame, the software should
update the data for the corresponding transmit object and send it
out.
Transmitting an RTR Frame
1. The software must setup a Tx object with the RTR bit in
MnCTL[0] set to ‘1’.
2. The software sets the object enable bit (OBJ_EN) which will
enable the object to participate in pre–arbitration.
3. After the object wins pre–arbitration, an RTR frame will be sent
out with a ‘1’ in the RTR bit position
.
4. At the end of a successful RTR transmission, the OBJ_EN bit will
be cleared. An interrupt could be generated if it is enabled.
5. It is possible for an incoming message, with CAN ID Matching
that of the transmitting RTR object, to arrive while the
transmitting RTR object is in pre–arbitration, or even during
transmission. In this case, the OBJ_EN bit of the transmitting
RTR object will be cleared to ‘0’, but no interrupt will be
generated.
Data integrity issues
The data stored in the message buffer area can be accessed both
by the CPU and by the DMA engine. Measures have been taken to
ensure that the application does not read data from an object as it is
being updated by the DMA. This is especially important if receive
interrupts have been disabled or have not been responded to before
a new message could have arrived. The general principle is,
When DMA is accessing the buffer, the CPU should NOT attempt
to read from and write to the buffer.
When CPU is accessing the buffer, the DMA is still allowed to
access the buffer. When this happens the CPU should be able to
detect and abandon the data read.
Using the Semaphore Bits, SEM1 and SEM0
A three–state semaphore is used to signal whether a given buffer is:
1. Ready for CPU to read
2. Being accessed by DMA (therefore not ready for CPU read)
3. Being read by CPU
The semaphore is encoded by two semaphore bits, SEM1 and
SEM0, which are in bit positions [5] and [4] of the Frame Info byte,
the first byte of the receive buffer.
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PXAC37KBBD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce
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PXAC37KFA/00,512 功能描述:IC XA MCU 16BIT 32K OTP 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:XA 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤(pán) 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
PXAC37KFBD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:XA 16-bit microcontroller family 32K/1024 OTP CAN transport layer controller 1 UART, 1 SPI Port, CAN 2.0B, 32 CAN ID Filters, transport layer co-proce
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