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參數(shù)資料
| 型號(hào)： | PWS740 |
| 英文描述： | Distributed Multi-Channel Isolated DC-TO-DC CONVERTER |
| 中文描述： | 分布式多通道隔離型DC - DC轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 117K |
| 代理商： | PWS740 |
PWS740
5
PIN DESCRIPTIONS OF
PWS740-1 DRIVER
+V
IN
, RETURN, AND GND
These are the power supply pins. The ground connection,
RETURN, for the N-channel MOSFET sources is brought
out separately from the ground connection for the oscillator/
driver chip. The waveform of the FETs’ ground return
current (and also the current in the V
DRIVE
line) is an 800kHz
sawtooth. A capacitor between +V
IN
and the FET ground
provides a bypass for the AC portion of this current.
The power should never be instantaneously interrupted to
the PWS740 system (i.e., a break in the line from V+, either
accidental or by means of a series switch). Normal power-
down of the V+ supply is not considered instantaneous.
Should a rapid break in input power occur, however, the
transformers’ voltage will rapidly increase to maintain cur-
rent flow. Such a voltage spike may damage the PWS740-1.
The bypass capacitors at the +V
IN
pin of the PWS740-1 and
the V
DRIVE
pins of the transformers provide a path for the
primary current if power is interrupted; however, total pro-
tection requires some type of bidirectional 1A voltage clamp-
ing at the +V
IN
pin. A low cost SA20A TransZorb
from
General Semiconductor
(1)
or equivalent, which will clamp
the +V
IN
pin between –0.6V and +23V, is recommended.
T
O
AND T
O
These pins are the drains of the N-channel MOSFET switches
which drive all the transformer primaries in parallel. The
signals on these pins are 400kHz complementary square
waves with twice the amplitude of the voltage at +V
IN
. It is
these lines that allow the power to be distributed to the
individual high voltage isolation transformers. Without proper
printed circuit board layout techniques, these lines could
generate interference to analog circuits. See the next section
on PCB layout.
ENABLE
A high TTL logic level on this pin activates the MOSFET
driver circuitry. A low TTL level applied to the ENABLE
pin shuts down all drive to the transformers and the output
voltages go to zero (only the oscillator is unaffected). For
continuous operation, the ENABLE pin can be left open or
tied to a voltage between +2V and +V.
SYNCHRONIZATION
The SYNC pin is used to synchronize up to eight PWS740-
1 oscillators. Synchronization is useful to prevent beat fre-
quencies in the supply voltages. The SYNC pins of two or
more PWS740-1s are tied together to force all units to the
same frequency of oscillation. The resultant frequency is
slightly higher than that of the highest unsynchronized unit.
If this feature is not required, leave the SYNC pin open. The
SYNC pin is sensitive to capacitance loading. 150pF or less
is recommended. Also external parasitic capacitive feedback
between either T
O
and the SYNC pin can cause unstable
operation (commonly seen as jitter in the T
O
outputs). Keep
SYNC connections and T
O
lines as physically isolated as
possible. Avoid shorting the SYNC pin directly to ground or
supply potentials; otherwise, damage may result.
Figure 1 shows a method for synchronizing a greater number
of PWS740-1 drivers. One unit is chosen as the master. Its
synchronization signal, buffered by a high-speed unity gain
amplifier can synchronize up to 20 slave units. Pin 1 of each
slave unit must be grounded to assure synchronization.
Minimize capacitive coupling between the buffered sync
line and the outputs of the drivers, especially at the end of
long lines. Capacitance to ground is not critical, but total
stray capacitance between the sync line and switching out-
puts should be kept below 50pF. Where extreme line lengths
are needed, such as between printed circuit boards, addi-
tional OPA633 buffers may be added to keep drive imped-
ance at an acceptably low value. Because of temperature-
influenced shifts in the switching levels, best operation of
this circuit will occur when differences in ambient tempera-
tures between the PWS740-1 drivers are minimized, typi-
cally within a 35
°
C range.
(1) General Semiconductor Industries Inc., 2001 W. 10th Place, Tempe AZ 85281,
602-968-3101.
TransZorb
General Semiconductor Industries Inc.
FIGURE 1. Master/Slave Synchronization of Multiple
PWS740 Drivers.
OPA633
6
8 Channels
4
Typical at
25°C
200ns
400kHz
8 Channels
8 Channels
NC
1
2
3.0V
2.5V
1
1
Slave
740-1
#1
Slave
740-1
#20
4
2
6
4
2
6
Master
740-1
+15V
–15V
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