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參數(shù)資料
| 型號： | PW-82520R1-231Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 1 A, DMA41 |
| 封裝： | DIP-41 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 219K |
| 代理商： | PW-82520R1-231Q |
7
Data Device Corporation
www.ddc-web.com
PW-82520R
F-03/06-0
During the first half of the PWM cycle the MOSFET's, Phase A
upper and Phase B lower, are turned on to provide current into
the phases.
During the second half of the PWM cycle the drive is in dead
time, all transistors are turned off, the motor current continues to
flow in the same direction through the device diodes, until it
decays to zero.
Current flowing in to and out of the phases produces a net torque
in one direction.
MAJOR ADVANTAGES
The advantage of a complementary 4-quadrant drive over a
standard 4-quadrant drive is that it provides holding torque dur-
ing a zero current command. The motor current at 50% duty
cycle is simply the magnetizing current of the motor winding.
Using the complementary 4-quadrant technique allows the motor
direction to be defined by the duty cycle.
Relative to a given switch pair, i.e. Phase A upper and Phase B
lower, a duty cycle greater than 50% will result in a clockwise
rotation whereas a duty cycle less than 50% will result in a count-
er clockwise rotation. Therefore, with the use of average current
mode control, direction can be controlled without the use of a
direction bit and the current can be controlled through zero in a
very precise and linear fashion.
The PW-82520R contains all the circuitry required to close an
average current mode control loop around a complementary 4-
quadrant drive. The PW-82520R use of average current mode
control simplifies the control loop by eliminating the need for
slope compensation and by eliminating the pole created by the
motor inductance. Slope compensation and the pole created by
the motor inductance are two limitations normally associated
with implementing standard 4 quadrant current mode controls.
FIGURE 3B. STANDARD 4 QUADRANT DRIVE
PWM CYCLE
FUNCTIONAL PIN DESCRIPTIONS
VBUS+A, VBUS+B, VBUS+C
The VBUS+ supply is the power source for the motor phases.
The normal operating voltage is 28Vdc and may vary from +18
to +70Vdc with respect to VBUS-. The power stage MOSFETS in
the hybrid have an absolute maximum VBUS+ supply voltage
rating of 100V. The user must supply sufficient external capaci-
tance or circuitry to prevent the bus supply from exceeding the
maximum recommended voltages at the hybrid power terminals
under any condition.
POWER-ON SEQUENCE (IMPORTANT!)
The VBUS+ should be applied at least 50ms after VDD and VEE
to allow the internal analog circuitry to stabilize. If this is not pos-
sible, the hybrid must be powered up in the "disabled" mode.
VBUS-
This is the high current ground return for VBUS+. This point must
be closely connected to SUPPLY GND for proper operation of
the current loop.
VCC (+5V SUPPLY) AND VCC RTN
These inputs are used to power the digital circuitry of the hybrid.
VDR (+15V SUPPLY)
This input is used to power the gate driver circuitry for the output
MOSFETs. There is no power consumption from VDR when the
hybrid is disabled.
VDD (+5V TO +15V SUPPLY), AND
VEE (-5V TO -15V SUPPLY)
These inputs can vary from ±5V to ±15V as long as they are
symmetrical. VDD and VEE are used to power the small signal
analog circuitry of the hybrid. Please note that using ±5V supply
will reduce the quiescent power consumption by approximately
60% when compared to ±15V operation.
UA
LA
UB
LB
0
Drive Switches and Phase Current vs. Time
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Phase
Current
Switc
hes
Time (quarter phase)
12
3
4
1
2
3
4
UA
LA
UB
LB
0
Drive Switches and Phase Current vs. Time
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Switc
hes
Phase
Current
Time (half phase)
1
2
3
4
FIGURE 3A. COMPLEMENTARY 4-QUADRANT DRIVE
PWM CYCLE
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