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參數(shù)資料
| 型號： | PW-82520N0-370 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 運動控制電子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, 18 A, DMA41 |
| 封裝： | HYBRID, DIP-41 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 773K |
| 代理商： | PW-82520N0-370 |
R8C/3JC Group
2. Central Processing Unit (CPU)
REJ03B0302-0100 Rev.1.00
Page 11 of 54
May 25, 2010
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1
CPU Registers
R2
b31
b15
b8b7
b0
Data registers (1)
Address registers (1)
R3
R0H (high-order of R0)
R2
R3
A0
A1
INTBH
b15
b19
b0
INTBL
FB
Frame base register (1)
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
Interrupt table register
b19
b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL
D
Z
S
B
O
I
U
b15
b0
b15
b0
b15
b0
b8
b7
Note:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
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