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參數(shù)資料
| 型號： | PUMA67E4001A-15E |
| 元件分類： | PROM |
| 英文描述： | 128K X 32 EEPROM 5V MODULE, 150 ns, CQMA68 |
| 封裝： | CERAMIC, LCC-68 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 235K |
| 代理商： | PUMA67E4001A-15E |
ISSUE 4.3 : January 2001
PUMA 2/67E4001/A/B - 12/15/20
3
AC Test Conditions
Output Test Load
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 10ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* V
CC=5V±10%
Write Cycle
Parameter
Symbol
min
typ
max
Unit
Write Cycle Time
t
WC
--
10
ms
Address Set-up Time
t
AS
0-
-
ns
Address Hold Time
t
AH
50
-
ns
Output Enable Set-up Time
t
OES
0-
-
ns
Output Enable Hold Time
t
OEH
0-
-
ns
Chip Select Set-up Time
t
CS
0-
-
ns
Chip Select Hold Time
t
CH
0-
-
ns
Write Pulse Width
t
WP
100
-
ns
Write Enable High Recovery
t
WPH
50
-
ns
Data Set-up Time
t
DS
50
-
ns
Data Hold Time
t
DH
0-
-
ns
Byte Load Cycle
t
BLC
-
150
s
AC OPERATING CONDITIONS
Read Cycle
12
15
20
Parameter
Symnbol
min
max
min
max
min
max Unit
Read Cycle Time
t
RC
120
-
150
-
200
-
ns
Address Access Time
t
AA
-
120
-
150
-
200
ns
Chip Select Access Time
t
CS
-
120
-
150
-
200
ns
Output Enable Access Time
t
OE
0
60
0
70
0
80
ns
CS or OE to Output Float (2)
t
DF
0
60
0
70
0
80
ns
Output Hold from Address Change
t
OH
0-
0
-
ns
Notes: (1) t
HZ max. and tOLZ max. are measured with CL = 5pF, from the point when Chip Select or Output Enable return high
(whichever occurs first) to the time when the outputs are no longer driven. t
HZ and tOHZ are shown for reference only:
they are characterized and not tested.
(2) This parameter is characterised and is not 100% tested.
645
100pF
I/O Pin
1.76V
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