參數(shù)資料
型號： PTPS659109A1RSL
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 81/89頁
文件大?。?/td> 941K
代理商： PTPS659109A1RSL
PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
Bits
Field Name
Description
Type
Reset
1
VMBHI_IT_MSK
VBAT > VMBHI event interrupt mask.
RW
1
When 0, enable the device automatic switch on at BACKUP to OFF or
NOSUPPLY to OFF device state transition (EEPROM bit)
0
VMBDCH_IT_MSK
Setting supply state control though EN3 signal
RW
0
Table 75. INT_STS2_REG
Address Offset
0x52
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
7
6
5
4
3
2
1
0
Reserved
GPIO0_F_IT
GPIO0_R_IT
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
W1 to Clr
1
GPIO0_F_IT
GPIO0 falling edge detection interrupt status
RW
0
W1 to Clr
0
GPIO0_R_IT
GPIO0 rising edge detection interrupt status
RW
0
W1 to Clr
Table 76. INT_MSK2_REG
Address Offset
0x53
Physical Address
Instance
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
Reserved
GPIO0_F_IT_MSK
GPIO0_R_IT_MSK
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
1
GPIO0_F_IT_MSK
GPIO_CKSYNC falling edge detection interrupt mask.
RW
0
GPIO0_R_IT_MSK
GPIO_CKSYNC rising edge detection interrupt mask.
RW
0
Table 77. GPIO0_REG
Address Offset
0x60
Physical Address
Instance
Description
GPIO0 configuration register
82
Copyright 2010, Texas Instruments Incorporated
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