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參數(shù)資料
| 型號(hào)： | PTPS659108A1RSLR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48 |
| 文件頁(yè)數(shù)： | 28/89頁(yè) |
| 文件大小： | 941K |
| 代理商： | PTPS659108A1RSLR |
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PRODUCTPREVIEW
SWCS046-016
SCLSR_EN1
VDIG1
1.2 V
VPLL
1.8 V
SCLSR_EN2
NRESPWON
TdVEN
TdEN
Switch-on sequence
Swtich-off sequence
Device on
TdEN
TdSOFF2
TdEN
Low-power mode
SWCS046-017
SCLSR_EN2
VDD2/VFB2
VDD1/VFB1
1.2 V
SCLSR_EN1
NRESPWON
Low-power mode
PFM (pulse skipping) mode
Switch-on sequence
Swtich-off sequence
Device on
PWM mode
SW1
TdOEN
0 V
TdVDDEN
TdOEN
TdEN
3.3 V
TdVDDEN
TdSOFF2
TdEN
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
Table 7. Device Turn-on/off with Rising/Falling Input Voltage, Timing Characteristics (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdONPWHOLD: delay to set high PWRHOLD signal or
tPDINT1 –
DEV_ON control bit after NRESPWON released to
tDSONT =
ms
keep on the supplies
984
TdbVMBDCH: Main Battery voltage = VMBDCH
3 × tCK32k
4 × tCK32k
s
threshold to INT1 falling edge delay
= 94
= 125
TdbVMBLO: Main Battery voltage = VMBLO threshold
3 × tCK32k
4 × tCK32k
s
to NRESPWON falling edge delay
= 94
= 125
Power supplies state control though the SCLSR_EN1 and SDASR_EN2 signals.
Figure 7. LDO Type Supplies State Control Though SCLSR_EN1 and SCLSR_EN2
Note: Register setting: VDIG1_EN1 = 1, VPLL_EN2 = 1, and VPLL_KEEPON = 1
Figure 8. VDD1 and VDD2 Supplies State Control Though SCLSR_EN1 and SCLSR_EN2
Note: Register setting: VDD2_EN2 = 1, VDD1_EN1 = 1, VDD1_KEEPON = 1, VDD1_PSKIP = 0, and SEL[6:0] =
hex00 in VDD2_SR_REG
Table 8. Supplies State Control Though SCLSR_EN1 and SCLSR_EN2 Timing Characteristics
Parameter
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdEN: NREPSWON to supply state
change delay, SCLSR_EN1 or
0
ms
SCLSR_EN2 driven
tdEN: SCLSR_EN1 or
SCLSR_EN2 edge to supply state
1 × tCK32k = 31
s
change delay
34
Copyright 2010, Texas Instruments Incorporated
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