參數(shù)資料
型號(hào)： PTPS659108A1RSL
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY SUPPORT CKT, PQCC48
封裝： 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48
文件頁數(shù)： 22/89頁
文件大?。?/td> 941K
代理商： PTPS659108A1RSL
PRODUCTPREVIEW
SWCS046-018
PWRHOLD
VIO/VFBIO
VAUX1
VDD2/VFB2
VDD1/VFB1
VPLL
VDAC
VAUX2
VMMC
CLK32KOUT
NRESPWRON
t
dSOFF2
t
dSON1
1.8 V
3.3 V
t
dSON2
t
dSON3
1.2 V
1.8 V
t
dSON4
t
dSON5
1.8 V
t
dSON6
t
dSON7
3.3 V
t
dSON8
t
dSOFF1
Switch-off sequence
t
: Switch-on sequence
dSONT
www.ti.com
SWCS046C – MARCH 2010 – REVISED JUNE 2010
Figure 2 shows the 00 Boot mode timing characteristics.
Figure 2. Boot Mode: BOOT1 = 0, BOOT0 = 0
Table 3 lists the 00 Boot mode timing characteristics.
Table 3. Boot Mode: BOOT1 = 0, BOOT0 = 0 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tdSON1
PWRHOLD rising edge to VIO, VAUX1 enable delay
66 × tCK32k = 2060
s
tdSON2
VIO to VDD2 enable delay
64 × tCK32k = 2000
s
tdSON3
VDD2 to VDD1 enable delay
64 × tCK32k = 2000
s
tdSON4
VDD1 to VPLL enable delay
64 × tCK32k = 2000
s
tdSON5
VPLL to VDAC,VAUX2 enable delay
64 × tCK32k = 2000
s
tdSON6
VDAC to VMMC enable delay
64 × tCK32k = 2000
s
VMMC to CLK32KOUT rising edge delay
64 × tCK32k = 2000
s
tdSON8
CLK32KOUT to NRESPWON rising edge delay
64 × tCK32k = 2000
s
tdSONT
Total switch-on delay
16
ms
PWRHOLD falling edge to NRESPWON falling edge
tdSOFF1
2 × tCK32k = 62.5
s
delay
tdSOFF1B
NRESPWON falling edge to CLK32KOUT low delay
3 × tCK32k = 92
s
PWRHOLD falling edge to supplies and reference
tdSOFF2
5 × tCK32k = 154
s
disable delay
Registers default setting: CK32K_CTRL = 1 (32-kHz RC oscillator is used), RTC_PWDN = 1 (RTC domain off),
IT_POL = 0 (INt2 interrupt flag active low), VMBHI_IT_MSK = 0 (automatic switch-on on Battery plug),
VMBCH_SEL = 11.
BOOT1 = 0, BOOT0 = 1
Table 4 provides details about the EEPROM setting for the BOOT modes. The power-up sequence for this boot
mode is provided in Figure 3.
Copyright 2010, Texas Instruments Incorporated
29
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