- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄69258 > PTPS659101A1RSL (TEXAS INSTRUMENTS INC) POWER SUPPLY SUPPORT CKT, PQCC48 PDF資料下載
參數(shù)資料
| 型號(hào)： | PTPS659101A1RSL |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48 |
| 文件頁(yè)數(shù)： | 81/89頁(yè) |
| 文件大小： | 941K |
| 代理商： | PTPS659101A1RSL |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)當(dāng)前第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)
PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
Bits
Field Name
Description
Type
Reset
1
VMBHI_IT_MSK
VBAT > VMBHI event interrupt mask.
RW
1
When 0, enable the device automatic switch on at BACKUP to OFF or
NOSUPPLY to OFF device state transition (EEPROM bit)
0
VMBDCH_IT_MSK
Setting supply state control though EN3 signal
RW
0
Table 75. INT_STS2_REG
Address Offset
0x52
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
7
6
5
4
3
2
1
0
Reserved
GPIO0_F_IT
GPIO0_R_IT
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
W1 to Clr
1
GPIO0_F_IT
GPIO0 falling edge detection interrupt status
RW
0
W1 to Clr
0
GPIO0_R_IT
GPIO0 rising edge detection interrupt status
RW
0
W1 to Clr
Table 76. INT_MSK2_REG
Address Offset
0x53
Physical Address
Instance
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
Reserved
GPIO0_F_IT_MSK
GPIO0_R_IT_MSK
Bits
Field Name
Description
Type
Reset
7:2
Reserved
Reserved bit
RW
0
1
GPIO0_F_IT_MSK
GPIO_CKSYNC falling edge detection interrupt mask.
RW
0
GPIO0_R_IT_MSK
GPIO_CKSYNC rising edge detection interrupt mask.
RW
0
Table 77. GPIO0_REG
Address Offset
0x60
Physical Address
Instance
Description
GPIO0 configuration register
82
Copyright 2010, Texas Instruments Incorporated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PTQA420033N2AD | 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE |
| PTQA420033P2AZ | 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE |
| PTQA420025P2AD | 1-OUTPUT 75 W DC-DC REG PWR SUPPLY MODULE |
| PTQA420025N2AD | 1-OUTPUT 75 W DC-DC REG PWR SUPPLY MODULE |
| PTQA420025N2AZ | 1-OUTPUT 75 W DC-DC REG PWR SUPPLY MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PTPS659109A1RSL | 制造商:Texas Instruments 功能描述: |
| PTPS6591102A2ZRCR | 制造商:TI 功能描述:TPS65911 |
| PTPS6591102ZRC | 制造商:TI 功能描述:TPS65911 |
| PTPS6591104A2ZRCR | 制造商:TI 功能描述:TPS65911 |
| PTPS659110A2ZRC | 制造商:TI 功能描述:TPS65911 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。