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參數(shù)資料
| 型號(hào)： | PTH12060YAZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT DC-DC REG PWR SUPPLY MODULE |
| 封裝： | ROHS COMPLIANT, DIP-10 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 823K |
| 代理商： | PTH12060YAZT |
www.ti.com
PTHXX060
(Top View)
1
2
10 9
8
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5
4
3
PTH03060Y
PTH05060Y, PTH12060Y
SLTS222A–MARCH 2004–REVISED OCTOBER 2005
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
VIN
2
The positive input voltage power node to the module, which is referenced to common GND.
This is the common ground connection for the VIN and VTT power connections. It is also the 0-VDC reference
GND
1, 7
for the control inputs.
The module senses the voltage at this input to regulate the output voltage, VTT. The voltage at VREF is also
the reference voltage for the system bus receiver comparators. It is normally set to precisely half the bus
VREF
8
driver supply voltage (VDDQ÷ 2), using a resistor divider. The Thevenin impedance of the network driving the
VREF pin should not exceed 500 . See the Typical DDR Application Diagram in the Application Information
section for reference.
This is the regulated power output from the module with respect to the GND node, and the tracking
termination supply for the application data and address buses. It is precisely regulated to the voltage applied
VTT
6
to the module's VREF input, and is active active about 20 ms after a valid input source is applied to the
module. Once active it will track the voltage applied at VREF.
The sense input allows the regulation circuit to compensate for voltage drop between the module and the
Vo Sense
5
load. For optimal voltage accuracy Vo Sense should be connected to VTT.
The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a low-level
ground signal to this input turns off the output voltage, VTT. Although the module is inhibited, a voltage, VDDQ
will be present at the output terminals, fed through the DDR memory. When the Inhibit is active, the input
Inhibit
3
current drawn by the regulator is significantly reduced. If the Inhibit pin is left open circuit, the module will
produce an output whenever a valid input source is applied. See the Typical DDR Application Diagram in the
Application Information section for reference.
N/C
4, 9, 10
No connect
4
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