參數(shù)資料
型號(hào)： PTH12060WAD
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源模塊
英文描述： 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
封裝： ROHS COMPLIANT, DIP-10
文件頁(yè)數(shù)： 24/29頁(yè)
文件大?。?/td> 1040K
代理商： PTH12060WAD
ELECTRICAL CHARACTERISTICS
SLTS217H – MAY 2003 – REVISED DECEMBER 2008 .................................................................................................................................................... www.ti.com
TA = 25C; VI = 12 V; VO = 1.8 V; CI = 560 F, CO = 0 F, and IO = IOmax (unless otherwise stated)
PTH12060L
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Over
ΔVadj range
85°C, 200 LFM airflow
0
10
(1)
IO
Output current
A
25°C, natural convention
0
10
(1)
VI
Input voltage range
Over IO range
10.8
13.2
V
VO tol
Set-point voltage tolerance
±2
(2)
%VO
ΔRegtemp
Temperature variation
–40°C < TA < 85°C
±0.5
%VO
ΔRegline
Line regulation
Over VI range
±10
mV
ΔRegload
Load regulation
Over IO range
±12
mV
ΔRegtot
Total output variation
Includes set-point, line, load, –40°C
≤ TA ≤ 85°C
±3
%VO
ΔVadj
Output voltage adjust range
Over VI range
0.8
1.8
V
RSET = 130 , VO = 1.8 V
88%
RSET = 3.57 k, VO = 1.5 V
87%
η
Efficiency
IO = 8 A
RSET = 12.1 k, VO = 1.2 V
84%
RSET = 32.4 k, VO = 1 V
82%
RSET = open circuit, VO = 0.8 V
81%
VO > 1 V
20
(3)
20-MHz bandwidth,
VO ripple (peak-to-peak)
mVPP
with CO2 = 10 F ceramic
VO ≤ 1 V
30
(3)
IO trip
Overcurrent threshold
Reset, followed by auto-recovery
20
A
ttr
1 A/s load step, 50 to 100%
Recovery time
70
S
Transient response
IOmax,
VO over/undershoot
100
mV
ΔVtr
CO1 = 330 F
VOadj
Margin up/dow adjust
±5%
IILmargin
Margin input current (pins 9/10)
Pin to GND
–8
(4)
A
IILtrack
Track input current (pin 8)
Pin to GND
–0.11
(5)
mA
dVtrack/dt
Track slew rate capability
CO ≤ CO (max)
1
V/ms
VI increasing
9.5
10.4
UVLO
Under-voltage lockout
V
VI decreasing
8.8
9
VIH
Input high voltage, Referenced to GND
Open
(5)
V
VIL
Inhibit Control (pin 3)
Input low voltage, Referenced to GND
–0.2
0.5
IIL
Input low current, Pin 3 to GND
0.24
mA
II
Input standby current
Inhibit (pin 3) to GND, Track (pin 8) open
10
mA
f s
Switching frequency
Over VI and IO ranges
200
250
300
kHz
CI
External input capacitance
560
(6)
F
Nonceramic
0
330
(7)
5500
(8)
Capacitance value
F
CO
External output capacitance
Ceramic
0
300
Equivalent series resistance (nonceramic)
4
(9)
m
Per Bellcore TR-332
6.4
MTBF
Reliability
10
6 Hr
50% stress, TA = 40°C, ground benign
(1)
See SOA curves or consult factory for appropriate derating.
(2)
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1% with 100 ppm/°C or better temperature stability.
(3)
The peak-to-peak output ripple voltage is measured with an external 10-F ceramic capacitor. See the standard application schematic.
(4)
A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
(5)
This control pin has an internal pull-up to the input voltage VI. If it is left open-circuit, the module operates when input power is applied.
A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an
external pull-up on this pin. For further information, see the application information section.
(6)
A 560-F input capacitor are required for proper operation. The electrolytic capacitor must be rated for a minimum of 1050 mA rms of
ripple current.
(7)
An external output capacitor is not required for basic operation. Adding 330 F of distributed capacitance at the load improves the
transient response.
(8)
This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a
voltage supervisor, CO(max) is reduced to 2200 F. See the application notes for further guidance.
(9)
This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 7 m
as the minimum when using max-ESR values
to calculate.
4
Copyright 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): PTH12060W/L
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