參數(shù)資料
型號(hào): PT7M7446YTAE
廠商: PERICOM SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝: LEAD FREE, MO-178AA, SOT-23, 5 PIN
文件頁(yè)數(shù): 7/11頁(yè)
文件大?。?/td> 542K
代理商: PT7M7446YTAE
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PT0289(07/07)
Ver: 0
5
Preliminary Data Sheet
PT7M7443-52
P Supervisory Circuit
Figure 6 PT7M7449~7452 Calculating the
Monitored Threshold Voltages
The PT7M7443~7452 /RESET output is pulse asserted
once for the reset timeout period after each valid manual
reset input condition. At least one manual reset input must
be released (go high) and then be driven low for the
extended setup period before /RESET asserts again.
Internal timing circuitry debounces low-to-high manual
reset logic transitions, so no external circuitry is required.
Figure 9 illustrates the single manual reset function of the
PT7M443/7444 single-voltage monitors, and Figure 10
represents the dual manual reset function of the
PT7M7445/7446 and PT7M7449/7450.
The PT7M7447/7448 and PT7M7451/7452 include both
an extended setup period and immediate setup period
manual reset inputs. A low-to-high MR2 rising edge
transition immediately pulse asserts the /RESET output for
the
reset
timeout
period
(140ms
min).
If
the
PT7M7447/7448 and PT7M7451/7452 MR2 input senses
another rising edge before the end of the 140ms timeout
period (Figure 11), the internal timer clears and begins
counting again. If no rising edges are detected within the
210ms timeout period, /RESET deasserts. The high-to-low
transition on MR2 input is internally debounced for 210ms
to ensure that there are no false /RESET assertions when
MR2 is driven from high to low (Figure 12). The MR2
input can be used for system test purposes or smart-card-
detect applications (see Applications Information section).
Application Information
Adjustable Input Voltage (RSTIN)
The PT7M7449~7452 monitor the voltage on RSTIN using an
adjustable reset threshold set with an external resistor voltage-divider
(see Figure 14). Use the following formula to calculate the externally
monitored voltage (VMON-TH):
() 2
2
1
R
V
RSTIN
TH
MON
+
×
=
Where VMON-TH is the desired reset threshold voltage and VTH-RSTIN is
the reset input threshold (0.63V). Resistors R1 and R2 can have very
high values to minimize current consumption because of low leakage
currents. Set R2 to some conveniently high value (250k, for
example), and calculate R1 based on the desired reset threshold
voltage, using the following formula:
()
×
=
1
2
1
RSTIN
TH
MON
V
R
Figure 4 PT7M7447/7448/7451/7452 MR2 Assertion
Debouncing Timing Diagram
Figure 5 PT7M7447/7448/7451/7452 MR2 Deassertion
Debouncing Timing Diagram
相關(guān)PDF資料
PDF描述
PT7M7452TTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
PT7M7445MTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
PT7M7444TTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
PT7M7444YTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
PT7M7452LTAE 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
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