
Application Notes
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Using the Margin Up/Down Controls on the
PT5800 & PT5810 Regulator Series
The PT5800 & PT5810 series of integrated switching
regulator modules incorporate Margin Up* (pin 4) and
Margin Dn* (pin 3) control inputs. These controls allow the
output voltage set point to be momentarily adjusted 1,
either up or down, by a nominal 5%. This provides a
convenient method for dynamically testing the load
circuit’s power supply voltage over its operating margin
or range. Note that the ±5% change is also applied to any
adjustment of the output voltage, if made, using the Vo
Adjust (pin 1).
The 5% adjustment is made by driving the appropriate
margin control input directly to the ground reference at
Sense(-) (pin 8) 2. An low-leakage open-drain device, such as
a MOSFET or a p-channel JFET is recommended for this
purpose. Adjustments of less than 5% can also be accom-
modated by adding series resistors to the control inputs
(See Figure 6-1). The value of the resistor can be selected
from Table 6-1, or calculated using the following formula.
Resistor Value Calculation
To reduce the margin adjustment to something less than
5%, series padding resistors are required (See RD and
RU in Figure 6-1). For the same amount of adjustment,
the resistor value calculated for RU and RD will be the
same. The formulas is as follows.
RU/RD =
499
– 99.8
k
%
Where
% = The desired amount of margin adjust in
percent.
Notes:
1. The Margin Up* and Margin Dn* controls were not
intended to be activated simultaneously. If they are
their affects on the output voltage may not completely
cancel, resulting in a slight shift in the output voltage
set point.
2. When possible use the Sense(-) (pin 8) as the ground
reference. This will produce a more accurate adjustment
of the output voltage at the load circuit terminals. GND
(pins 9-13) can be used if the Sense(-) pin is connected
to GND near the regulator.
C
out
+
C
in
+5V
GND
MargDn
L
O
A
D
Q
2
Sense(–)
+V
OUT
GND
PT5800
18
14–17
8
29–13
5, 6, 7
V
OUT
V
IN
GND
SNS(+)
SNS(–)
INHIBIT*
Q
1
4
3
MARG
DN*
MARG
UP*
+
MargUp
0V
+V
o
R
D
R
U
0V
Figure 6-1; Margin Up/Down Application Schematic
Table 6-1; Margin Up/Down Resistor Values
PADDING RESISTOR VALUES
% Adjust
RU / RD
5
0.0k
4
24.9k
3
66.5k
2
150.0k
1
397.0k
PT5800 & PT5810 Series