參數(shù)資料
    型號(hào): PSD9545V70MIT
    廠商: 意法半導(dǎo)體
    元件分類: 基準(zhǔn)電壓源/電流源
    英文描述: Advanced PFC/PWM Combination Controllers 20-PDIP -40 to 105
    中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
    文件頁(yè)數(shù): 36/110頁(yè)
    文件大?。?/td> 1737K
    代理商: PSD9545V70MIT
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    36/110
    Complex PLD (CPLD)
    The CPLD can be used to implement system logic
    functions, such as loadable counters and shift reg-
    isters, system mailboxes, handshaking protocols,
    state machines, and random logic. The CPLD can
    also be used to generate three External Chip Se-
    lect (ECS0-ECS2), routed to Port D.
    Although External Chip Select (ECS0-ECS2) can
    be produced by any Output Macrocell (OMC),
    these three External Chip Select (ECS0-ECS2) on
    Port D do not consume any Output Macrocells
    (OMC).
    As shown in
    Figure 13., page 34
    , the CPLD has
    the following blocks:
    24 Input Macrocells (IMC)
    16 Output Macrocells (OMC)
    Macrocell Allocator
    Product Term Allocator
    AND Array capable of generating up to 137
    product terms
    Four I/O Ports.
    Each of the blocks are described in the sections
    that follow.
    The Input Macrocells (IMC) and Output Macrocells
    (OMC) are connected to the PSD internal data bus
    and can be directly accessed by the MCU. This
    enables the MCU software to load data into the
    Output Macrocells (OMC) or read data from both
    the Input and Output Macrocells (IMC and OMC).
    This feature allows efficient implementation of sys-
    tem logic and eliminates the need to connect the
    data bus to the AND Array as required in most
    standard PLD macrocell architectures.
    Figure 15. Macrocell and I/O Port
    I/O PORTS
    CPLD MACROCELLS
    INPUT MACROCELLS
    LATCHED
    ADDRESS OUT
    MUX
    M
    M
    M
    M
    D
    D
    Q
    Q
    Q
    G
    D
    Q D
    WR
    WR
    PDR
    DATA
    PALLOCATOR
    DIR
    SELECT
    INPUT
    PFROM OTHER
    MACROCELLS
    POLARITY
    PROUP TO 10
    CLOCK
    PR
    DI LD
    D/T
    CK
    CL
    Q
    SELECT
    PT CLEAR
    PT
    GLOBAL
    PT OUTPUT ENABLE (OE)
    MACROCELL FEEDBACK
    I/O PORT INPUT
    ALE/AS
    PT INPUT LATCH GATE/CLOCK
    MCU LOAD
    PT PRESET
    MCU DATA IN
    /REG
    SELECT
    MACTO
    IALLOC.
    OCPLD
    TO OTHER I/O PORTS
    P
    P
    MCU ADDRESS/DATA BUS
    MOUT TO
    MCU
    CDATA
    A
    CPLD OUTPUT
    I/O PIN
    AI02874
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