1. 參數(shù)資料
      型號: PSD954370MT
      廠商: 意法半導(dǎo)體
      英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
      中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
      文件頁數(shù): 18/110頁
      文件大小: 1737K
      代理商: PSD954370MT
      PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
      18/110
      PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
      Table
      6
      shows the offset addresses to the PSD
      registers relative to the CSIOP base address. The
      CSIOP space is the 256 bytes of address that is al-
      located by the user to the internal PSD registers.
      Table
      7
      provides brief descriptions of the registers
      in CSIOP space. The following section gives a
      more detailed description.
      Table 6. I/O Port Latched Address Output Assignments (Note1)
      Note: 1. See the section entitled
      I/O PORTS, page 51
      , on how to enable the Latched Address Output function.
      2. N/A = Not Applicable
      Table 7. Register Address Offset
      Note: 1. Other registers that are not part of the I/O ports.
      MCU
      Port A
      Port B
      Port A (3:0)
      Port A (7:4)
      Port B (3:0)
      Port B (7:4)
      8051XA (8-bit)
      N/A
      Address a7-a4
      Address a11-a8
      N/A
      80C251 (page mode)
      N/A
      N/A
      Address a11-a8
      Address a15-a12
      All other 8-bit multiplexed
      Address a3-a0
      Address a7-a4
      Address a3-a0
      Address a7-a4
      8-bit non-multiplexed bus
      N/A
      N/A
      Address a3-a0
      Address a7-a4
      Register Name
      Port A Port B Port C Port D Other
      1
      Description
      Data In
      00
      01
      10
      11
      Reads Port pin as input, MCU I/O input mode
      Control
      02
      03
      Selects mode between MCU I/O or Address Out
      Data Out
      04
      05
      12
      13
      Stores data for output to Port pins, MCU I/O
      output mode
      Direction
      06
      07
      14
      15
      Configures Port pin as input or output
      Drive Select
      08
      09
      16
      17
      Configures Port pins as either CMOS or Open
      Drain on some pins, while selecting high slew rate
      on other pins.
      Input Macrocell
      0A
      0B
      18
      Reads Input Macrocells
      Enable Out
      0C
      0D
      1A
      1B
      Reads the status of the output enable to the I/O
      Port driver
      Output Macrocells
      AB
      20
      20
      READ – reads output of macrocells AB
      WRITE – loads macrocell flip-flops
      Output Macrocells
      BC
      21
      21
      READ – reads output of macrocells BC
      WRITE – loads macrocell flip-flops
      Mask Macrocells AB
      22
      22
      Blocks writing to the Output Macrocells AB
      Mask Macrocells BC
      23
      23
      Blocks writing to the Output Macrocells BC
      Primary Flash
      Protection
      C0
      Read only – Primary Flash Sector Protection
      Secondary Flash
      memory Protection
      C2
      Read only – PSD Security and Secondary Flash
      memory Sector Protection
      JTAG Enable
      C7
      Enables JTAG Port
      PMMR0
      B0
      Power Management Register 0
      PMMR2
      B4
      Power Management Register 2
      Page
      E0
      Page Register
      VM
      E2
      Places PSD memory areas in Program and/or
      Data space on an individual basis.
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