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  • 參數(shù)資料
    型號(hào): PSD935G1-B-12MI
    廠商: 意法半導(dǎo)體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
    文件頁(yè)數(shù): 27/91頁(yè)
    文件大?。?/td> 488K
    代理商: PSD935G1-B-12MI
    PSD9XX Family
    PSD935G2
    26
    The
    PSD935G2
    Functional
    Blocks
    (cont.)
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    Sec7_Prot
    Sec6_Prot
    Sec5_Prot
    Sec4_Prot
    Sec3_Prot
    Sec2_Prot
    Sec1_Prot Sec0_Prot
    Flash Protection Register
    9.1.1.10.2 Reset Instruction
    The Reset instruction consists of one write cycle (see Table 8). It can also be optionally
    preceded by the standard two write decoding cycles (writing AAh to AAAh and 55h to
    554h).
    The Reset instruction must be executed after:
    1. Reading the Flash Protection status or Flash ID using the Flash instruction.
    2. When an error condition occurs (DQ5 goes high) during a Flash programming or erase
    cycle.
    The Reset instruction will reset the Flash to normal Read Mode immediately. However, if
    there is an error condition (DQ5 goes high), the Flash memory will return to the Read
    Mode in 25 μSeconds after the Reset instruction is issued.
    The Reset instruction is ignored when it is issued during a Flash programming or Bulk
    Erase cycle. The Reset instruction will abort the on going sector erase cycle and return the
    Flash memory to normal Read Mode in 25 μSeconds.
    9.1.1.10.3 Reset Pin Input
    The reset pulse input from the pin will abort any operation in progress and reset the Flash
    memory to Read Mode. When the reset occurs during a programming or erase cycle, the
    Flash memory will take up to 25 μSeconds to return to Read Mode. It is recommended that
    the reset pulse (except power on reset, see Reset Section) be at least 25 μSeconds such
    that the Flash memory will always be ready for the MCU to fetch the boot code after reset
    is over.
    Bit Definitions:
    Sec<i>_Prot
    Sec<i>_Prot
    1 = Main Flash Sector <i> is write protected.
    0 = Main Flash Sector <i> is not write protected.
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    Security_
    Bit
    *
    *
    *
    Sec3_Prot
    Sec2_Prot
    Sec1_Prot Sec0_Prot
    Flash Boot Protection Register
    Bit Definitions:
    Sec<i>_Prot
    Sec<i>_Prot
    Security_Bit
    1 = Flash Boot Sector <i> is write protected.
    0 = Flash Boot Sector <i> is not write protected.
    0 = Security Bit in device has not been set.
    1 = Security Bit in device has been set.
    Table 10. Sector Protection/Security Bit Definition
    *:
    Not used.
    相關(guān)PDF資料
    PDF描述
    PSD935G1-B-12U Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G1-B-12UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G1-B-15B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G1-B-15B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G1-B-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
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