參數(shù)資料
型號: PSD935F3V-15UI
廠商: 意法半導(dǎo)體
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述: 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù): 11/91頁
文件大?。?/td> 488K
代理商: PSD935F3V-15UI
PSD9XX Family
PSD935G2
10
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
PE3
74
I/O
Port E, PE3. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. TDO output for JTAG/ISP interface.
Port E, PE4. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. TSTAT output for the ISP interface.
4. Rdy/Bsy — for in-circuit Parallel Programming.
Port E, PE5. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. TERR active low output for ISP interface.
Port E, PE6. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. Vstby — SRAM standby voltage input for battery
backup SRAM
Port E, PE7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address output.
3. Vbaton — battery backup indicator output. Goes high when
power is drawn from an external battery.
Port F, PF0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Input to the PLD.
3. Latched address outputs.
4. As address A0-3 inputs in 80C51XA mode
5. As data bus port (D0-7) in non-multiplexed bus configuration
Port G, PG0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O — standard output or input port.
2. Latched address outputs.
CMOS
or Open
Drain
PE4
75
I/O
CMOS
or Open
Drain
PE5
76
I/O
CMOS
or Open
Drain
PE6
77
I/O
CMOS
or Open
Drain
PE7
78
I/O
CMOS
or Open
Drain
PF0-PF7
31-38
I/O
CMOS
or Open
Drain
PG0-PG7 21-28
I/O
CMOS
or Open
Drain
GND
8,30,
49,50,
70
9,29,
69
V
CC
Table 5.
PSD935G2
Pin
Descriptions
(cont.)
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