參數(shù)資料
型號： PSD935F3V-15JI
廠商： 意法半導體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù)： 38/91頁
文件大?。?/td> 488K
代理商： PSD935F3V-15JI
PSD935G2
PSD9XX Family
37
The
PSD935G2
Functional
Blocks
(cont.)
9.3 Microcontroller Bus Interface
The
“
no-glue logic
”
PSD935G2 Microcontroller Bus Interface can be directly connected to
most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their
bus types and control signals are shown in Table 14. The MCU interface type is
specified using the PSDsoft.
9.3.1. PSD935G2 Interface to a Multiplexed Bus
Figure 13 shows an example of a system using a microcontroller with a 8-bit multiplexed
bus and a PSD935G2. The ADIO port on the PSD935G2 is connected directly to the
microcontroller address/data bus. ALE latches the address lines internally. Latched
addresses can be brought out to Port E, F or G. The PSD935G2 drives the ADIO data bus
only when one of its internal resources is accessed and the RD input is active. Should the
system address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional
address inputs.
9.3.2. PSD935G2 Interface to a Non-Multiplexed Bus
Figure 14 shows an example of a system using a microcontroller with a 8-bit
non-multiplexed bus and a PSD935G2. The address bus is connected to the ADIO Port,
and the data bus is connected to Port F. Port F is in tri-state mode when the PSD935G2
is not accessed by the microcontroller. Should the system address bus exceed sixteen
bits, Ports A, B or C may be used for additional address inputs.
Data
Bus
Width
MCU
CNTL0
CNTL1
CNTL2
PC7
*
*
*
*
*
*
*
DBE
*
*
*
*
PD0**
ADIO0
PF3-PF0 PF7-PF4
*
A3-A0
*
*
*
*
*
*
D3-D0
*
*
D3-D0
8031/8051
80C51XA
80C251
80C251
80198
68HC11
68HC05C0
68HC912
Z80
Z8
68330
M37702M2
8
8
8
8
8
8
8
8
8
8
8
8
WR
WR
WR
WR
WR
R/W
WR
R/W
WR
R/W
R/W
R/W
RD
RD
PSEN
RD
RD
E
RD
E
RD
DS
DS
E
PSEN
PSEN
*
PSEN
*
*
*
*
*
*
*
*
ALE
ALE
ALE
ALE
ALE
AS
AS
AS
*
AS
AS
ALE
A0
A4
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
*
*
*
*
*
*
*
*
D7-D4
*
*
D7-D4
Table 14. Microcontrollers and their Control Signals
*
*
Unused CNTL2 pin can be configured as PLD input. Other unused pins (PD3-0, PA3-0) can be
**
configured for other I/O functions.
**
ALE/AS input is optional for microcontrollers with a non-multiplexed bus
相關PDF資料
PDF描述
PSD935F3V-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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