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參數(shù)資料
| 型號： | PSD935F3V-15J |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存儲系統(tǒng) |
| 文件頁數(shù)： | 19/91頁 |
| 文件大?。?/td> | 488K |
| 代理商： | PSD935F3V-15J |
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PSD9XX Family
PSD935G2
18
The
PSD935G2
Functional
Blocks
(cont.)
FS0-7
or
CSBOOT0-3
Instruction
Cycle 1 Cycle 2 Cycle 3
Cycle 4
Cycle5
Cycle 6
Cycle 7
Read (Note 5)
1
“
Read
”
RA RD
Read Main Flash ID
(Notes 6,13)
1
AAh
@555h
55h
90h
@555h
“
Read
”
ID
@x01h
@AAAh
Read Sector Protection
(Notes 6,8,13)
1
AAh
@555h
55h
90h
@555h
“
Read
”
00h or 01h
@x02h
@AAAh
Program a Flash Byte
1
AAh
@555h
55h
A0h
@555h
PD@PA
@AAAh
Erase One Flash Sector
1
AAh
@555h
55h
80h
@555h
AAh
@555h
55h
30h
@SA
30h
@AAAh
@AAAh
@next SA
(Note 7)
Erase Flash Block
(Bulk Erase)
1
AAh
@555h
55h
80h
@555h
AAh
@555h
55h
10h
@555h
@AAAh
@AAAh
Suspend Sector Erase
(Note 11)
1
B0h
@xxxh
Resume Sector Erase
(Note 12)
1
30h
@xxxh
Reset (Note 6)
1
F0 @ any
address
Unlock Bypass
1
AAh
@555h
55h
20h
@555h
@AAAh
Unlock Bypass Program
(Note 9)
1
A0h
@xxxh
PD@PA
Unlock Bypass Reset
(Note 10)
1
90h
@xxxh
00h
@xxxh
Table 9. Instructions
X
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WR#
(CNTL0) pulse.
PD = Data to be programmed at location PA. Data is latched o the rising edge of WR# (CNTL0) pulse.
SA = Address of the sector to be erased or verified. The chip select (FS0-7 or CSBOOT0-3) of the sector to be
erased must be active (high).
= Don
’
t Care.
NOTES:
1.
All bus cycles are write bus cycle except the ones with the
“
read
”
label.
2.
All values are in hexadecimal.
3.
FS0-7 and CSBOOT0-3 are active high and are defined in PSDsoft.
4.
Only Address bits A11-A0 are used in Instruction decoding. A15-12 (or A16-A12) are don
’
t care.
5.
No unlock or command cycles required when device is in read mode.
6.
The Reset command is required to return to the read mode after reading the Flash ID, Sector Protect status
or if DQ5 (error flag) goes high.
7.
Additional sectors to be erased must be entered within 80μs.
8.
The data is 00h for an unprotected sector and 01h for a protected sector. In the fourth cycle, the sector chip
select is active and (A1 = 1, A0 = 0).
9.
The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the
Unlock Bypass mode.
11. The system may read and program functions in non-erasing sectors, read the Flash ID or read the Sector
Protect status, when in the Erase Suspend mode. The erase Suspend command is valid only during a sector
erase operation.
12. The Erase Resume command is valid only during the Erase Suspend mode.
13. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the
instruction is intended. The MCU must fetch, for example, codes from the secondary block when reading the
Sector Protection Status of the main Flash.
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| PSD935F3V-15JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
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| PSD935F3V-15MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
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| PSD935G2V-90U | 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD835G2V-90U RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD954F2-90J | 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD854F2-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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