參數(shù)資料
型號: PSD935F3V-15B81I
廠商: 意法半導(dǎo)體
英文描述: Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
中文描述: 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù): 16/91頁
文件大?。?/td> 488K
代理商: PSD935F3V-15B81I
PSD935G2
PSD9XX Family
15
9.0
The
PSD935G2
Functional
Blocks
As shown in Figure 1, the PSD935G2 consists of six major types of functional blocks:
J
Memory Blocks
J
PLD Blocks
J
Bus Interface
J
I/OPorts
J
Power Management Unit
J
JTAG-ISP Interface
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD935G2 has the following memory blocks:
The main Flash memory
Secondary Flash memory
SRAM.
The memory select signals for these blocks originate from the Decode PLD (DPLD) and
are user-defined in PSDsoft.
Table 7 summarizes which versions of the PSD935G2 contain which memory blocks.
Main Flash
Secondary Flash
Block Size
Device
Flash Size
Sector Size
Sector Size
SRAM
PSD935G2
512KB
64KB
32KB
8KB
8KB
Table 7. Memory Blocks
9.1.1 Main Flash and Secondary Flash Memory Description
The main Flash memory block is divided evenly into eight sectors. The secondary Flash
memory is divided into four sectors of eight Kbytes each. Each sector of either memory
can be separately protected from program and erase operations.
Flash memory may be erased on a sector-by-sector basis and programmed word-by-word.
Flash sector erasure may be suspended while data is read from other sectors of memory
and then resumed after reading.
During a program or erase of Flash, the status can be output on the Rdy/Bsy pin of Port
PE4. This pin is set up using PSDsoft.
9.1.1.1 Memory Block Selects
The decode PLD in the PSD935G2 generates the chip selects for all the internal memory
blocks (refer to the PLD section). Each of the eight Flash memory sectors have a
Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the
four Secondary Flash memory sectors have a Select signal (CSBOOT0-3) which can
contain up to three product terms. Having three product terms for each sector select signal
allows a given sector to be mapped in different areas of system memory. When using a
microcontroller (80C51) with separate Program and Data space, these flexible select
signals allow dynamic re-mapping of sectors from one space to the other before and after
IAP.
相關(guān)PDF資料
PDF描述
PSD935F3V-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15MI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15U Configurable Memory System on a Chip for 8-Bit Microcontrollers
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