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  • 參數(shù)資料
    型號(hào): PSD935F1-A-70MI
    廠商: 意法半導(dǎo)體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
    文件頁(yè)數(shù): 47/91頁(yè)
    文件大小: 488K
    代理商: PSD935F1-A-70MI
    PSD9XX Family
    PSD935G2
    46
    The
    PSD935G2
    Functional
    Blocks
    (cont.)
    9.4 I/OPorts
    There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each of the ports
    is eight bits except Port D, which is 4 bits. Each port pin is individually user configurable,
    thus allowing multiple functions per port. The ports are configured using PSDsoft or by the
    microcontroller writing to on-chip registers in the CSIOP address space.
    The topics discussed in this section are:
    General Port Architecture
    Port Operating Modes
    Port Configuration Registers
    Port Data Registers
    Individual Port Functionality.
    9.4.1 General Port Architecture
    The general architecture of the I/O Port is shown in Figure 20. Individual Port architectures
    are shown in Figures 21 through 23. In general, once the purpose for a port pin has been
    defined, that pin will no longer be available for other purposes. Exceptions will be noted.
    As shown in Figure 20, the ports contain an output multiplexer whose selects are driven
    by the configuration bits in the Control Registers (Ports E, F and G only) and PSDsoft
    Configuration. Inputs to the multiplexer include the following:
    J
    Output data from the Data Out Register
    J
    Latched address outputs
    J
    GPLD outputs (External Chip Selects)
    The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
    read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
    microcontroller. The Data Out and Micro
    Cell outputs, Direction and Control Registers,
    and port pin input are all connected to the PDB.
    The contents of these registers can be altered by the microcontroller. The PDB feedback
    path allows the microcontroller to check the contents of the registers.
    9.4.2 Port Operating Modes
    The I/O Ports have several modes of operation. Some modes can be defined using
    PSDsoft, some by the microcontroller writing to the Registers in CSIOP space, and some
    by both. The modes that can only be defined using PSDsoft must be programmed into the
    device and cannot be changed unless the device is reprogrammed. The modes that can be
    changed by the microcontroller can be done so dynamically at run-time. The PLD I/O,
    Data Port, Address Input, and MCU Reset modes are the only modes that must be defined
    before programming the device. All other modes can be changed by the microcontroller at
    run-time.
    Table 16 summarizes which modes are available on each port. Table 19 shows how and
    where the different modes are configured. Each of the port operating modes are described
    in the following subsections.
    相關(guān)PDF資料
    PDF描述
    PSD935F1-A-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935F1-B-20B81 Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 20pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Sn60 Coated; Body Dimensions: 0.080&quot; x 0.050&quot; x 0.055&quot;; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
    PSD935F1-B-20B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935F1-B-20J Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935F1-B-20JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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