參數資料
型號： PSD934F2
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統)
中文描述： 在8片位微控制器可配置存儲系統（用于8位微控制器的可配置存儲器系統）
文件頁數： 63/94頁
文件大?。?/td> 477K
代理商： PSD934F2
Preliminary Information
PSD9XX Family
59
The
PSD9XX
Functional
Blocks
(cont.)
9.5.3 Reset and Power On Requirement
9.5.3.1 Power On Reset
Upon power up the PSD9XX requires a reset pulse of tNLNH-PO (minimum 1 ms) after
V
CC
is steady. During this time period the device loads internal configurations, clears
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD9XX remains in the reset state for an additional tOPR (maximum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD9XX Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of a byte being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when V
CC
is below VLKO.
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 25 shows the timing of the power on and warm reset.
OPERATING LEVEL
POWER ON RESET
V
CC
RESET
tNLNH
–
PO
tOPR
tNLNH-A
tNLNH
tOPR
WARM
RESET
Figure 25. Power On and Warm Reset Timing
9.5.3.3
I/OPin, Register and PLD Status at Reset
Table 33 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the V
CC
ramps up to operating level. Once the PLD
is active, the state of the outputs are determined by the PLD equations.
相關PDF資料
PDF描述
PSD935G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲器可編程外設)
PSD935G2 CONFIGURABLE MEMORY SYSTEM ON A CHIP FOR 8-BIT MICROCONTROLLERS
PSD935G2V 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA package; Similar to IRHM57160 with optional Total Dose Rating of 300kRads
PSD935G2-B-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F2-B-12B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關代理商/技術參數
參數描述
PSD934F2-15J 功能描述:SPLD - 簡單可編程邏輯器件 5V 2M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD934F290J 制造商:WSI 功能描述:
PSD934F2-90J 功能描述:SPLD - 簡單可編程邏輯器件 PLCC-52 5V 2M 90NS RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2-90M 功能描述:SPLD - 簡單可編程邏輯器件 5V 2M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD934F2V-15J 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 2M 150ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*