- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368267 > PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging PDF資料下載
參數(shù)資料
| 型號： | PSD913F2V |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging |
| 中文描述： | 可配置的存儲(chǔ)系統(tǒng)級芯片的8位微控制器 |
| 文件頁數(shù)： | 31/94頁 |
| 文件大小： | 463K |
| 代理商： | PSD913F2V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
PSD913F1
Preliminary
30
Level 1
SRAM, I/O
Level 2
EEPROM Memory
Highest Priority
Lowest Priority
Level 3
Flash Memory
Figure 7. Priority Level of Memory and I/OComponents
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,
80C251, 80C51XA, and the C500 family, have separate address spaces for code memory
(selected using PSEN) and data memory (selected using RD). Any of the memories within
the PSD913F1 can reside in either space or both spaces. This is controlled through manip-
ulation of the VM register that resides in the PSD
’
s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, I may wish to have SRAM and Flash in Data Space at boot, and EEPROM in
Program Space at boot, and later swap EEPROM and Flash. This is easily done with
the VM register by using PSDsoft to configure it for boot up and having the microcontroller
change it when desired.
Table 12 describes the VM Register.
Bit 7*
Bit 6*
Bit 5*
Bit 4
FL_Data EE_Data
Bit 3
Bit 2
FL_Code
Bit 1
EE_Code SRAM_Code
Bit 0
*
*
*
0 = RD
can
’
t
access
Flash
0 = RD
can
’
t
access
EEPROM
0 = PSEN
can
’
t
access
Flash
0 = PSEN
can
’
t
access
EEPROM
0 = PSEN
can
’
t
access
SRAM
*
*
*
1 = RD
access
Flash
1 = RD
access
EEPROM
1 = PSEN
access
Flash
1 = PSEN
access
EEPROM
1 = PSEN
access
SRAM
Table 12. VM Register
NOTE:
Bits 5-7 are not used, should set to
“
0
”
.
The
PSD913F1
Functional
Blocks
(cont.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD913F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
| PSD934F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
| PSD913F2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
| PSD934F2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng)) |
| PSD935G2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲(chǔ)器可編程外設(shè)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913F2V-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12J1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 3.3 V |
| PSD913F2V-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。