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    參數(shù)資料
    型號: PSD853F2-90
    廠商: 意法半導(dǎo)體
    英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    中文描述: Flash在系統(tǒng)可編程(ISP)的周邊8位MCU,5V的
    文件頁數(shù): 71/110頁
    文件大?。?/td> 1737K
    代理商: PSD853F2-90
    71/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    INITIAL DELIVERY STATE
    When delivered from ST, the PSD device has all
    bits in the memory and PLDs set to ’1.’ The PSD
    Configuration Register bits are set to ’0.’ The code,
    configuration, and PLD logic are loaded using the
    programming procedure. Information for program-
    ming the device is available directly from ST.
    Please contact your local sales representative.
    Table 35. JTAG Enable Register
    Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config-
    uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is
    used to enable the JTAG signals.
    Bit 0
    JTAG_Enable
    0 = off JTAG port is disabled.
    1 = on JTAG port is enabled.
    Bit 1
    X
    0
    Not used, and should be set to zero.
    Bit 2
    X
    0
    Not used, and should be set to zero.
    Bit 3
    X
    0
    Not used, and should be set to zero.
    Bit 4
    X
    0
    Not used, and should be set to zero.
    Bit 5
    X
    0
    Not used, and should be set to zero.
    Bit 6
    X
    0
    Not used, and should be set to zero.
    Bit 7
    X
    0
    Not used, and should be set to zero.
    相關(guān)PDF資料
    PDF描述
    PSD854F3-12 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD854F3-15 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD854F3-20 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD854F3-90 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    PSD854F3V-12 Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    PSD853F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD854F2-15J 制造商:STMicroelectronics 功能描述:4556DIE2HR - Trays