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    參數(shù)資料
    型號(hào)： PSD8533V90JT
    廠商： 意法半導(dǎo)體
    英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
    中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
    文件頁(yè)數(shù)： 25/110頁(yè)
    文件大?。?/td> 1737K
    代理商： PSD8533V90JT
    25/110
    PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
    PROGRAMMING FLASH MEMORY
    Flash memory must be erased prior to being pro-
    grammed. A byte of Flash memory is erased to all
    1s (FFh), and is programmed by setting selected
    bits to ’0.’ The MCU may erase Flash memory all
    at once or by-sector, but not byte-by-byte. Howev-
    er, the MCU may program Flash memory byte-by-
    byte.
    The primary and secondary Flash memories re-
    quire the MCU to send an instruction to program a
    byte or to erase sectors (see
    Table 9., page 21
    ).
    Once the MCU issues a Flash memory Program or
    Erase instruction, it must check for the status bits
    for completion. The embedded algorithms that are
    invoked inside the PSD support several means to
    provide status to the MCU. Status may be checked
    using any of three methods: Data Polling, Data
    Toggle, or Ready/Busy (PC3).
    Data Polling
    Polling on the Data Polling Flag Bit (DQ7) is a
    method of checking whether a Program or Erase
    cycle is in progress or has completed. Figure
    7
    shows the Data Polling algorithm.
    When the MCU issues a Program instruction, the
    embedded algorithm within the PSD begins. The
    MCU then reads the location of the byte to be pro-
    grammed in Flash memory to check status. The
    Data Polling Flag Bit (DQ7) of this location be-
    comes the complement of b7 of the original data
    byte to be programmed. The MCU continues to
    poll this location, comparing the Data Polling Flag
    Bit (DQ7) and monitoring the Error Flag Bit (DQ5).
    When the Data Polling Flag Bit (DQ7) matches b7
    of the original data, and the Error Flag Bit (DQ5)
    remains ’0,’ the embedded algorithm is complete.
    If the Error Flag Bit (DQ5) is '1,' the MCU should
    test the Data Polling Flag Bit (DQ7) again since
    the Data Polling Flag Bit (DQ7) may have changed
    simultaneously with the Error Flag Bit (DQ5, see
    Figure
    7
    ).
    The Error Flag Bit (DQ5) is set if either an internal
    time-out occurred while the embedded algorithm
    attempted to program the byte or if the MCU at-
    tempted to program a '1' to a bit that was not
    erased (not erased is logic '0').
    It is suggested (as with all Flash memories) to read
    the location again after the embedded program-
    ming algorithm has completed, to compare the
    byte that was written to the Flash memory with the
    byte that was intended to be written.
    When using the Data Polling method during an
    Erase cycle, Figure
    7
    still applies. However, the
    Data Polling Flag Bit (DQ7) is '0' until the Erase cy-
    cle is complete. A 1 on the Error Flag Bit (DQ5) in-
    dicates a time-out condition on the Erase cycle; a
    0 indicates no error. The MCU can read any loca-
    tion within the sector being erased to get the Data
    Polling Flag Bit (DQ7) and the Error Flag Bit
    (DQ5).
    PSDsoft Express generates ANSI C code func-
    tions which implement these Data Polling algo-
    rithms.
    Figure 7. Data Polling Flowchart
    READ DQ5 & DQ7
    at VALID ADDRESS
    START
    READ DQ7
    FAIL
    PASS
    AI01369B
    D=
    DATA
    YES
    NO
    YES
    NO
    DQ5
    = 1
    D=
    DATA
    YES
    NO
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    參數(shù)描述
    PSD853F2-70J 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
    PSD853F2-70M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
    PSD853F2-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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