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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD835G3V-C-12U

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
中文描述：
在8片位微控制器可配置存儲(chǔ)系統(tǒng)

    

    
文件頁(yè)數(shù)：
73/110頁(yè)

    

    
文件大小：
570K

    

    
代理商：
PSD835G3V-C-12U


    

    

    

	
    
    
    

    
    
	
    PSD8XX Family 
    PSD835G2
    72
    The 
    PSD835G2
    Functional
    Blocks
    (cont.)
    9.6.1  Standard JTAG Signals (cont.)
    The PSD835G2 supports JTAG-ISP commands, but not Boundary Scan. ST's 
    PSDsoft software tool and FlashLink JTAG programming cable implement these JTAG-ISC
    commands. 
    9.6.2  JTAG Extensions
    TSTAT and TERR are two JTAG extension signals enabled by a JTAG command 
    received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to
    speed programming and erase functions by indicating status on PSD pins instead of 
    having to scan the status out serially using the standard JTAG channel. See Application
    Note 54.
    TERR will indicate if an error has occurred when erasing a sector or programming in 
    Flash memory. This signal will go low (active) when an error condition occurs, and stay 
    low until a special JTAG command is executed or a chip reset pulse is received after an
    “
    ISC-DISABLE
    ”
     command.
    TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will
    be high when the PSD835G2 device is in read array mode (Flash memory and Boot Block
    contents can be read). TSTAT will be low when Flash memory programming or erase
    cycles are in progress, and also when data is being written to the Flash Boot Block.
    TSTAT and TERR can be configured as open-drain type signals with a JTAG command.
    9.6.3   Security and Flash Memories Protection
    When the security bit is set, the device cannot be read on a device programmer or through 
    the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed. 
    All other program/erase/verify commands are blocked. Full chip erase returns the part to a
    non-secured blank state. The Security Bit can be set in PSDsoft.
    All Flash Memory and Boot sectors can individually be sector protected against erasures. 
    The sector protect bits can be set in PSDsoft.
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD835G3V-C-12UI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-C-15B81
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-C-15B81I
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-C-15J
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G3V-C-15JI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD853F2-70J
功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 70ns

 RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24

    

    
PSD853F2-70M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 70ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90J
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90JI
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
PSD853F2-90M
功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns

 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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