參數(shù)資料
型號： PSD835G3-C-15J
廠商： 意法半導體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù)： 14/110頁
文件大?。?/td> 570K
代理商： PSD835G3-C-15J
PSD835G2
PSD8XX Family
13
8.0
Register Bit
Definition
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IMcell7
IMcell6
IMcell5
IMcell4
IMcell3
IMcell2
IMcell1
IMcell0
Input Micro
Cells – Ports A, B and C
Bit definitions: Read Only Registers
Read Input Micro
Cell[7:0] status on Ports A, B and C.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella7
Mcella6
Mcella5
Mcella4
Mcella3
Mcella2
Mcella1
Mcella0
Output Micro
Cells A Register
Bit definitions:
Write Register:
Load Micro
CellA[7:0] with 0 or 1.
Read Register:
Read Micro
CellA[7:0] output status.
Output Micro
Cells B Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb7
Mcellb6
Mcellb5
Mcellb4
Mcellb3
Mcellb2
Mcellb1
Mcellb0
Bit definitions:
Write Register:
Load Micro
CellB[7:0] with 0 or 1.
Read Register:
Read Micro
CellB[7:0] output status.
Mask Micro
Cells A Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcella7
Mcella6
Mcella5
Mcella4
Mcella3
Mcella2
Mcella1
Mcella0
Bit definitions:
Register Bit <j> to 0 = allow Micro
CellA<j> flip flop to be loaded by MCU (default).
Register Bit <j> to 1 = does not allow Micro
CellA<j> flip flop to be loaded by MCU.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mcellb7
Mcellb6
Mcellb5
Mcellb4
Mcellb3
Mcellb2
Mcellb1
Mcellb0
Mask Micro
Cells B Register
Bit definitions:
Register Bit <j> to 0 = allow Micro
CellB<j> flip flop to be loaded by MCU (default).
Register Bit <j> to 1 = does not allow Micro
CellB<j> flip flop to be loaded by MCU.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec7_Prot
Sec6_Prot
Sec5_Prot
Sec4_Prot
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Protection Register
Bit definitions: Read Only Register
Sec<i>_Prot
1 = Flash Sector <i> is write protected.
Sec<i>_Prot
0 = Flash Sector <i> is not write protected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
*
*
*
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Boot Protection Register
Bit definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Boot Block Sector <i> is write protected.
0 = Boot Block Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
相關PDF資料
PDF描述
PSD835G3-C-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-70B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-70B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-70J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G3V-70JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關代理商/技術參數(shù)
參數(shù)描述
PSD853F2-70J 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD853F2-70M 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90J 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90JI 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90M 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*