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| 型號(hào)： | PSD835G2-C-90J |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存儲(chǔ)系統(tǒng) |
| 文件頁(yè)數(shù)： | 75/110頁(yè) |
| 文件大?。?/td> | 570K |
| 代理商： | PSD835G2-C-90J |
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PSD8XX Family
PSD835G2
74
AC/DC
Parameters
The following tables describe the AD/DC parameters of the PSD8XX family:
J
DC Electrical Specification
J
AC Timing Specification
PLD Timing
–
Combinatorial Timing
–
Synchronous Clock Mode
–
Asynchronous Clock Mode
–
Input Micro
Cell Timing
Microcontroller Timing
–
Read Timing
–
Write Timing
–
Peripheral Mode Timing
–
Power Down and Reset Timing
Following are issues concerning the parameters presented:
J
In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that
the PSD8XX is in each mode. Also, the supply power is considerably different if the
Turbo bit is "OFF".
J
The AC power component gives the PLD, Flash memory, and SRAM mA/MHz
specification. Figures 32 and 32a show the PLD mA/MHz as a function of the number
of Product Terms (PT) used.
J
In the PLD timing parameters, add the required delay when Turbo bit is "OFF".
Figure 32. PLD ICC/FrequencyConsumption
(VCC= 5 V ± 10%)
0
10
20
30
40
60
70
80
90
100
110
V
CC
= 5V
50
0
10
15
5
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
I
C
TURBO ON (100%)
TURBO ON (25%)
TURBOOFF
TURBO OFF
PT 100%
PT 25%
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