參數(shù)資料
型號： PSD835G2-A-70MI
廠商： 意法半導(dǎo)體
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
中文描述： 在8片位微控制器可配置存儲系統(tǒng)
文件頁數(shù)： 61/110頁
文件大?。?/td> 570K
代理商： PSD835G2-A-70MI
PSD8XX Family
PSD835G2
60
The
PSD835G2
Functional
Blocks
(cont.)
9.4.4 Port Data Registers
The Port Data Registers, shown in Table 24, are used by the microcontroller to write data
to or read data from the ports. Table 24 shows the register name, the ports having each
register type, and microcontroller access for each register type. The registers are
described below.
9.4.4.1 Data In
Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input
is read through the Data In buffer.
9.4.4.2 Data Out Register
Stores output data written by the MCU in the MCU I/O output mode. The contents of the
Register are driven out to the pins if the Direction Register or the output enable
product term is set to “1”. The contents of the register can also be read back by the
microcontroller.
9.4.4.3 Output Micro
Cells (OMCs)
The CPLD OMCs occupy a location in the microcontroller’s address space. The
microcontroller can read the output of the OMCs. If the Mask Micro
Cell Register bits are
not set, writing to the Micro
Cell loads data to the Micro
Cell flip flops. Refer to the PLD
section for more details.
9.4.4.4 Mask Micro
Cell Register
Each Mask Register bit corresponds to an OMC flip flop. When the Mask Register bit
is set to a “1”, loading data into the OMC flip flop is blocked. The default value is “0” or
unblocked.
9.4.4.5 Input Micro
Cells (IMCs)
The IMCs can be used to latch or store external inputs. The outputs of the IMCs
are routed to the PLD input bus, and can be read by the microcontroller. Refer to the PLD
section for a detailed description.
9.4.4.6 Enable Out
The Enable Out register can be read by the microcontroller. It contains the output enable
values for a given port. A “1” indicates the driver is in output mode. A “0” indicates the
driver is in tri-state and the pin is in input mode.
Register Name
Port
MCU Access
Data In
A,B,C,D,E,F,G
Read – input on pin
Data Out
A,B,C,D,E,F,G
Write/Read
Output Micro
Cell
A,B
Read – outputs of Micro
Cells
Write – loading Micro
Cells Flip-Flop
Mask Micro
Cell
A,B
Write/Read – prevents loading into a given
Micro
Cell
Read – outputs of the Input Micro
Cells
Input Micro
Cell
A,B,C
Enable Out
A,B,C,F
Read – the output enable control of the port driver
Table 24. Port Data Registers
相關(guān)PDF資料
PDF描述
PSD835G2-A-70U Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2-A-70UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2-A-90B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2-A-90B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD835G2-A-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD835G2V-12UI 功能描述:靜態(tài)隨機存取存儲器 3.0V 4M 120ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD835G2V-90U 功能描述:靜態(tài)隨機存取存儲器 3.0V 4M 90ns RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
PSD853F2-70J 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24
PSD853F2-70M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 70ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD853F2-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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