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    參數(shù)資料
    

    


    


    
型號(hào)：
PSD835G2-20MI

    

    
廠商：
意法半導(dǎo)體

    

    
英文描述：
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
中文描述：
在8片位微控制器可配置存儲(chǔ)系統(tǒng)

    

    
文件頁(yè)數(shù)：
19/110頁(yè)

    

    
文件大?。?/td>
570K

    

    
代理商：
PSD835G2-20MI


    

    

    

	
    
    
    

    
    
	
    9.1.1.4   Memory Operation
    The main Flash and secondary Flash memories are addressed through the microcontroller 
    interface on the PSD835G2 device. The microcontroller can access these memories in one
    of two ways:
    J
     The microcontroller can execute a typical bus write or read 
    operation 
    just as it would 
    if accessing a RAM or ROM device using standard bus cycles.
    J
     The microcontroller can execute a specific 
    instruction 
    that consists of several write 
    and read operations. This involves writing specific data patterns to special addresses 
    within the Flash to invoke an embedded algorithm. These instructions are summarized 
    in Table 8.
    Typically, Flash memory can be read by the microcontroller using read operations, just 
    as it would read a ROM device. However, Flash memory can only be erased and 
    programmed with specific instructions. For example, the microcontroller cannot write a 
    single byte directly to Flash memory as one would write a byte to RAM. To program a byte
    into Flash memory, the microcontroller must execute a program instruction sequence, then
    test the status of the programming event. This status test is achieved by a read 
    operation or polling the Rdy/Busy pin (PE4).
    The Flash memory can also be read by using special instructions to retrieve particular
    Flash device information (sector protect status and ID).
    9.1.1.4.1  Instructions
    An instruction is defined as a sequence of specific operations. Each received byte is 
    sequentially decoded by the PSD and not executed as a standard write operation. The
    instruction is executed when the correct number of bytes are properly received and the
    time between two consecutive bytes is shorter than the time-out value. Some instructions
    are structured to include read operations after the initial write operations.
    The sequencing of any instruction must be followed exactly. Any invalid combination of
    instruction bytes or time-out between two consecutive bytes while addressing Flash 
    memory will reset the device logic into a read array mode (Flash memory reads like a
    ROM device).
    The PSD835G2 main Flash and secondary Flash support these instructions (see Table 8):
    J
     Erase memory by chip or sector
    J
     Suspend or resume sector erase
    J
     Program a byte
    J
     Reset to read array mode
    J
     Read Main Flash Identifier value
    J
     Read sector protection status
    J
     Bypass Instruction
    These instructions are detailed in Table 8. For efficient decoding of the instructions, the
    first two bytes of an instruction are the coded cycles and are followed by a command byte
    or confirmation byte. The coded cycles consist of writing the data AAh to address X555h
    during the first cycle and data 55h to address XAAAh during the second cycle (unless the
    Bypass Instruction feature is used. See 9.1.1.7). Address lines A15-A12 are don
    ’
    t care 
    during the instruction write cycles. However, the appropriate sector select signal (FSi or
    CSBOOTi) must be selected.
    The main Flash and the secondary Flash Block have the same set of instructions (except
    Read main Flash ID). The chip selects of the Flash memory will determine which Flash will
    receive and execute the instruction. The main Flash is selected if any one of the FS0-7 is
    active, and the secondary Flash Block is selected if any one of the CSBOOT0-3 is active.
    The 
    PSD835G2
    Functional
    Blocks
    (cont.)
    PSD8XX Family 
    PSD835G2 
    18
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
PSD835G2-20U
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G2-20UI
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G2-70B81
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G2-70B81I
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    
PSD835G2-70J
Configurable Memory System on a Chip for 8-Bit Microcontrollers

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
PSD835G2-70U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 70ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2-90U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2-90UI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 5.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2V-12UI
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 120ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
PSD835G2V-90U
功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 3.0V 4M 90ns

 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray

    

    
    
    
    
	
    	
    
    
     
     
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